Celebrity Inventors
Comic actor Danny Kaye received patent D166,807 for the co-design of "Blowout Toy or the Like". It's similar to one of those toys that unravels when you blow into at a birthday party except Kaye's has three blowouts going in different directions, not just one.
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| Number | Title | Issue Date |
| 7795103 | Bipolar transistors with depleted emitter This invention disclosed a novel method of fully depleted emitter so that the built-in potential between emitter and the base becomes lower and the charge storage between the emitter and base becomes small. This concept also applies to the diodes or rectifiers. With... | 09/14/2010 |
| 7605047 | Method for the integration of two bipolar transistors in a semiconductor body, semiconductor arrangement in a semiconductor body, and cascode circuit A method for the integration of two bipolar transistors in a semiconductor body, wherein, for the first bipolar transistor, a first emitter semiconductor region, a first base semiconductor region, and a first collector semiconductor region are produced. A recombinat... | 10/20/2009 |
| 7413958 | GaN-based permeable base transistor and method of fabrication An etched grooved GaN-based permeable-base transistor structure is disclosed, along with a method for fabrication of same. ... | 08/19/2008 |
| 7294543 | DRAM (Dynamic Random Access Memory) cells A DRAM cell with a self-aligned gradient P-well and a method for forming the same. The DRAM cell includes (a) a semiconductor substrate; (b) an electrically conducting region including a first portion, a second portion, and a third portion; (c) a first doped semicon... | 11/13/2007 |
| 7242012 | Lithography device for semiconductor circuit pattern generator General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor ... | 07/10/2007 |
| 7202531 | Semiconductor device A semiconductor device includes an output pad and a surge absorption unit formed above a semiconductor region of a first conductivity type. The surge absorption unit includes: a semiconductor island region of a second conductivity type; a buried layer of the second ... | 04/10/2007 |
| 7192838 | Method of producing complementary SiGe bipolar transistors Method of producing complementary SiGe bipolar transistors. In a method of producing complementary SiGe bipolar transistors, interface oxide layers (38, 58) for NPN and PNP emitters (44, 64), are separately formed and emitter polysilicon (40, 60... | 03/20/2007 |
| 7176099 | Hetero-junction bipolar transistor and manufacturing method thereof A hetero-junction bipolar transistor that satisfies high resistance required to avoid a potential breakdown includes: an n-type sub-collector layer 110 that is made of GaAs; an n-type first collector 121 that is made of a semiconductor material with a ... | 02/13/2007 |
| 7098113 | Method and system for providing a power lateral PNP transistor using a buried power buss A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer; an emitter region between the first and second collector regions. Therefore slots are placed in each of the regions. Accor... | 08/29/2006 |
| 7060583 | Method for manufacturing a bipolar transistor having a polysilicon emitter In the inventive method for manufacturing a bipolar transistor having a polysilicon emitter, a collector region of a first conductivity type and, adjoining thereto, a basis region of a second conductivity type will be generated at first. At least one layer of an ins... | 06/13/2006 |
| 7037799 | Breakdown voltage adjustment for bipolar transistors Devices and methods are disclosed related to a bipolar transistor device and methods of fabrication. A top region is formed at a surface of and within a base region. The top region is formed by implanting a dopant of an opposite conductivity to that of the base regi... | 05/02/2006 |
| 6933588 | High performance SCR-like BJT ESD protection structure In a NPN transistor electrostatic discharge (ESD) protection structure, certain parameters, including maximum lattice temperature, are improved by introducing certain process changes to provide for SCR-like characteristics during ESD events. A p+region is formed adj... | 08/23/2005 |
| 6893932 | Heterojunction bipolar transistor containing at least one silicon carbide layer A bipolar transistor includes a collector that is selected from the group SiC and SiC polytypes (4H, 6H, 15R, 3C . . . ), a base that is selected from the group Si, Ge and SiGe, at least a first emitter that is selected from the group Si, SiGe, SiC, amorphous-Si, am... | 05/17/2005 |
| 6891230 | Bipolar ESD protection structure The invention describes the fabrication and structure of an ESD protection device for integrated circuit semiconductor devices with improved ESD protection and resiliency. A vertical bipolar npn transistor forms the basis of the protection device. To handle the larg... | 05/10/2005 |
| 6838348 | Integrated process for high voltage and high performance silicon-on-insulator bipolar devices High-voltage bipolar transistors (30, 60) in silicon-on-insulator (SOI) integrated circuits are disclosed. In one disclosed embodiment, an collector region (28) is formed in epitaxial silicon (24, 25) disposed over a buried insulator layer (2... | 01/04/2005 |
| 6787427 | Method to fabricate SiGe HBTs with controlled current gain and improved breakdown voltage characteristics A method of fabricating a SiGe heterojunction bipolar transistor (HBT) is provided which results in a SiGe HBT that has a controllable current gain and improved breakdown voltage. The SiGe HBT having these characteristics is fabricated by forming an in-situ P-doped ... | 09/07/2004 |
| 6784064 | Heterojunction bipolar transistor and method of making heterojunction bipolar transistor A method of making a heterojunction bipolar transistor comprises the steps of: forming a mask layer on a compound semiconductor film by using a photomask for forming an emitter; and forming the emitter by wet-etching the compound semiconductor film by using the mask... | 08/31/2004 |
| 6759303 | Complementary vertical bipolar junction transistors fabricated of silicon-on-sapphire utilizing wide base PNP transistors A method for fabricating complementary vertical bipolar junction transistors of silicon-on-sapphire in fewer steps than required for true complimentary vertical bipolar junction transistors is disclosed. Initially a thin layer of silicon is grown on a sapphire subst... | 07/06/2004 |
| 6743691 | Semiconductor device and method for fabricating the same A bipolar transistor device with a large current capacity is formed by connecting a plurality of transistor elements to each other in parallel, each transistor element having a collector layer, a base layer, and an emitter layer formed respectively in a semiconducto... | 06/01/2004 |
| 6720625 | Bipolar ESD protection structure The invention describes the fabrication and structure of an ESD protection device for integrated circuit semiconductor devices with improved ESD protection and resiliency. A vertical bipolar npn transistor forms the basis of the protection device. To handle the larg... | 04/13/2004 |
| 6709941 | Method for manufacturing semiconductor device employing solid phase diffusion In a method for manufacturing a semiconductor device, an N type single-crystal silicon substrate having a first silicon oxide film and a P type poly-crystal silicon layer is provided. A silicon nitride film is formed on the P type poly-crystal silicon layer. A side ... | 03/23/2004 |
| 6682981 | Stress controlled dielectric integrated circuit fabrication General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a sem... | 01/27/2004 |
| 6673703 | Method of fabricating an integrated circuit A method of fabricating an integrated circuit including a monocrystalline silicon substrate, a layer of polycrystalline silicon on the top surface of the substrate and doped with at least two dopants with different rates of diffusion, in which method anne... | 01/06/2004 |
| 6664609 | High frequency differential amplification circuit with reduced parasitic capacitance Disclosed is a circuit layout of a differential amplification circuit that constitutes a Gilbert cell, in which two multiple finger bipolar transistors forming a differential amplifier are positioned substantially axially symmetrical to each other. The lo... | 12/16/2003 |
| 6563145 | Methods and apparatus for a composite collector double heterojunction bipolar transistor A compound collector double heterojunction bipolar transistor (CCHBT) incorporates a collector comprising two layers: a wide bandgap collector region (e.g., GaAs), and a narrow bandgap collector region (e.g., InGaP). The higher electric field is supported... | 05/13/2003 |
| 6559023 | Method of fabricating a semiconductor device with phosphorous and boron ion implantation, and by annealing to control impurity concentration thereof A method for manufacturing a semiconductor device constituting an JGHT is provided that allows to manufacture the device using an inexpensive wafer and with high yields, and achieves low losses. Specifically, after an emitter electrode is formed, a revers... | 05/06/2003 |
| 6544830 | Method of manufacturing a semiconductor device with multiple emitter contact plugs A semiconductor device, such as a BiCMOS, includes a bipolar transistor having at least an emitter region. An emitter electrode is formed on the emitter region. Further, a wiring pattern is formed over the emitter region. A plurality of contact plugs are ... | 04/08/2003 |
| 6524921 | Methods of forming bipolar transistor constructions The invention includes a bipolar transistor construction having a collector region, emitter region, and base region extending within a semiconductive material substrate. The construction further comprises separate access regions associated with the base r... | 02/25/2003 |
| 6503809 | Method and system for emitter partitioning for SiGe RF power transistors A power transistor includes a plurality of emitter regions and a plurality of base contacts. In order to decrease base resistance, each of the plurality of emitter regions is adjacent to at least four base contacts. The entire transistor includes multiple... | 01/07/2003 |
| 6472286 | Bipolar ESD protection structure The invention describes the fabrication and structure of an ESD protection device for integrated circuit semiconductor devices with improved ESD protection and resiliency. A vertical bipolar npn transistor forms the basis of the protection device. To hand... | 10/29/2002 |
| 6423603 | Method of forming a microwave array transistor for low-noise and high-power applications A transistor array including a plurality of transistors. Each transistor includes an emitter. An emitter region contact overlies each emitter region. At least one base region underlies each emitter region and is common to a plurality of transistors in the... | 07/23/2002 |
| 6236072 | Method and system for emitter partitioning for SiGe RF power transistors A power transistor includes a plurality of emitter regions and a plurality of base contacts. In order to decrease base resistance, each of the plurality of emitter regions is adjacent to at least four base contacts. The entire transistor includes multiple... | 05/22/2001 |
| 6228732 | Tunnel nitride for improved polysilicon emitter A method is disclosed for reproducibly and controllably enhancing the current gain of a bipolar junction transistor. Prior to depositing an extrinsic emitter region of polycrystalline silicon, the surface of a monocrystalline silicon substrate is nitridiz... | 05/08/2001 |
| 6211562 | Homojunction semiconductor devices with low barrier tunnel oxide contacts A homojunction bipolar transistor with performance characteristics similar to more costly heterojunction or retrograde base transistors. The high emitter resistivity found in prior homojunction devices is circumvented using a low work function material la... | 04/03/2001 |
| 6140694 | Field isolated integrated injection logic gate An integrated injection logic device is provided in which each collector of an I2L gate is isolated by a field oxide ("FOX"), or by other suitable isolation such as, for example, an isolation trench. The connection of the base to the collectors, between t... | 10/31/2000 |
| 6103584 | Uniform current density and high current gain bipolar transistor A bipolar transistor designed to support a substantially uniform current density in base and collector regions to prevent the characteristic early fall-off of bipolar transistor current gain, and to improve the forward safe operating area performance. The... | 08/15/2000 |
| 6004855 | Process for producing a high performance bipolar structure A process for producing a small shallow-depth high-performance bipolar structure having low parasitic capacitance is disclosed wherein an active base region of a P-type material is first defined in a substrate, a portion of which is of N-type material in ... | 12/21/1999 |
| 5869381 | RF power transistor having improved stability and gain Increased gain and improved stability are realized in using resistive emitter ballasting by including integrated capacitive elements in parallel with the resistive elements in the emitter circuit. A feature of the invention is an integrated capacitor stru... | 02/09/1999 |
| 5670417 | Method for fabricating self-aligned semiconductor component A self-aligned semiconductor component (10) includes a layer (14) having two openings (36, 38) and overlying a doped region (13) in a substrate (11). One (36) of the two openings (36, 38) is used to self-align a different doped region (22) and a portion (... | 09/23/1997 |
| 5455186 | Method for manufacturing an offset lattice bipolar transistor An architecture for producing multiple emitter vertical bipolar transistors which substantially eliminates the starved regions found in the standard lattice architecture. An "offset lattice" design is described in which the base contact segments in adjace... | 10/03/1995 |
