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| Number | Title | Issue Date |
| 8017489 | Field effect structure including carbon alloyed channel region and source/drain region not carbon alloyed A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device structure. The field effect device structure includes a gate electrode located over a channel region within a semiconductor substrate that separates a pl... | 09/13/2011 |
| 7919381 | Germanium substrate-type materials and approach therefor Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-contai... | 04/05/2011 |
| 7888225 | Method of manufacturing an electronic device including a PNP bipolar transistor A method of manufacturing an electronic device including a PNP bipolar transistor comprises forming a collector in a substrate, depositing a base layer and an emitter layer on the substrate, and growing a nitride interface layer on the base layer as a base current m... | 02/15/2011 |
| 7875522 | Silicon compatible integrated light communicator Various methods and devices are implemented using efficient silicon compatible integrated light communicators. According to one embodiment of the present invention, a semiconductor device is implemented for communicating light, such as by detecting, modulating or em... | 01/25/2011 |
| 7838376 | Non-destructive inline epi pattern shift monitor using selective epi Integrated circuits using buried layers under epitaxial layers present a challenge in aligning patterns for surface components to the buried layers, because the epitaxial material over the buried layer diminishes the visibility of and shifts the apparent position of... | 11/23/2010 |
| 7772078 | Germanium substrate-type materials and approach therefor Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-contai... | 08/10/2010 |
| 7405098 | Smooth surface liquid phase epitaxial germanium A method is provided for forming a liquid phase epitaxial (LPE) germanium (Ge)-on-insulator (GOI) thin-film with a smooth surface. The method provides a silicon (Si) wafer, forms a silicon nitride insulator layer overlying the Si wafer, and selectively etches the si... | 07/29/2008 |
| 7364976 | Selective etch for patterning a semiconductor film deposited non-selectively A method to selectively etch, and hence pattern, a semiconductor film deposited non-selectively is described. In one embodiment, a carbon-doped silicon film is deposited non-selectively such that the film forms an epitaxial region where deposited on a crystalline su... | 04/29/2008 |
| 7354835 | Method of fabricating CMOS transistor and CMOS transistor fabricated thereby In a method of fabricating a CMOS transistor, and a CMOS transistor fabricated according to the method, the characteristics of first and second conductivity type MOS transistors are both simultaneously improved. At the same time, the fabrication process is simplifie... | 04/08/2008 |
| 7354820 | Heterojunction bipolar transistor with dielectric assisted planarized contacts and method for fabricating A method for fabricating an HBT is disclosed, wherein successive emitter, base, collector and sub-collector epitaxial layers are deposited on a substrate, with the substrate being adjacent to the sub-collector layer. The epitaxial layers are etched to provide locati... | 04/08/2008 |
| 7291898 | Selective and non-selective epitaxy for base integration in a BiCMOS process and related structure According to one exemplary embodiment, a bipolar transistor includes an active area situated between first and second isolation regions in a substrate. The bipolar transistor further includes an epitaxial extension layer situated on the active area, where the epitax... | 11/06/2007 |
| 7271023 | Floating body germanium phototransistor A floating body germanium (Ge) phototransistor and associated fabrication process are presented. The method includes: providing a silicon (Si) substrate; selectively forming an insulator layer overlying the Si substrate; forming an epitaxial Ge layer overlying the i... | 09/18/2007 |
| 7265018 | Method to build self-aligned NPN in advanced BiCMOS technology The present invention provides a method of forming a self-aligned heterobipolar transistor (HBT) device in a BiCMOS technology. The method includes forming a raised extrinsic base structure by using an epitaxial growth process in which the growth rate between single... | 09/04/2007 |
| 7241700 | Methods for post offset spacer clean for improved selective epitaxy silicon growth A gate structure is formed overlying a substrate. A source/drain region of the substrate is exposed to a soluction comprising ammonium hydroxide, hydrogen peroxide, and deionized water to etch an upper-most semiconductor porton of the source/drain region. ... | 07/10/2007 |
| 7226844 | Method of manufacturing a bipolar transistor with a single-crystal base contact A method forms a bipolar transistor in a semiconductor substrate of a first conductivity type. The method includes: forming on the substrate a single-crystal silicon-germanium layer; forming a heavily-doped single-crystal silicon layer of a second conductivity type;... | 06/05/2007 |
| 7217665 | Method of plasma etching high-K dielectric materials with high selectivity to underlying layers A method of plasma etching a layer of dielectric material having a dielectric constant that is greater than four (4). The method includes exposing the dielectric material layer to a plasma comprising a hydrocarbon gas and a halogen containing gas. ... | 05/15/2007 |
| 7202514 | Self aligned compact bipolar junction transistor layout and method of making same The invention relates to a process of forming a bipolar junction transistor (BJT) that includes forming a topology over a substrate. Thereafter, a spacer is formed at the topology. A base layer is formed from epitaxial silicon above the spacer and at the topology. A... | 04/10/2007 |
| 7199017 | Methods of forming semiconductor circuitry The invention includes a method of forming semiconductor circuitry. A monocrystalline silicon substrate is provided, and a mask is formed which covers a first portion of the substrate and leaves a second portion uncovered. A trench is formed in the uncovered portion... | 04/03/2007 |
| 7195985 | CMOS transistor junction regions formed by a CVD etching and deposition sequence This invention adds to the art of replacement source-drain cMOS transistors. Processes may involve etching a recess in the substrate material using one equipment set, then performing deposition in another. Disclosed is a method to perform the etch and subsequent dep... | 03/27/2007 |
| 7192838 | Method of producing complementary SiGe bipolar transistors Method of producing complementary SiGe bipolar transistors. In a method of producing complementary SiGe bipolar transistors, interface oxide layers (38, 58) for NPN and PNP emitters (44, 64), are separately formed and emitter polysilicon (40, 60... | 03/20/2007 |
| 7169226 | Defect reduction by oxidation of silicon A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate materials which may be used as a template for strained Si is described. A silicon-on-insulator substrate with a very thin top Si layer is used as a template for compressively str... | 01/30/2007 |
| 7151035 | Semiconductor device and manufacturing method thereof A sidewall-insulation film 9 is provided on a side surface of a first opening portion 8a formed in a base extraction electrode 5B of a hetero-junction bipolar transistor, and a portion of the sidewall-insulation film 9 extends so a... | 12/19/2006 |
| 7141478 | Multi-stage EPI process for forming semiconductor devices, and resulting device The present invention is generally directed to a multi-stage epi process for forming semiconductor devices, and the resulting device. In one illustrative embodiment, the method comprises forming a first layer of epitaxial silicon above a surface of a semiconducting ... | 11/28/2006 |
| 7128846 | Process for producing group III nitride compound semiconductor A method including the steps of: modifying at least one part of a sapphire substrate by dry etching to thereby form any one of a dot shape, a stripe shape, a lattice shape, etc. as an island shape on the sapphire substrate; forming an AlN buffer layer on the sapphir... | 10/31/2006 |
| 7118981 | Method of fabricating an integrated silicon-germanium heterobipolar transistor and an integrated silicon-germanium heterobipolar transistor In a method of fabricating an integrated silicon-germanium heterobipolar transistor a silicon dioxide layer arranged between a silicon-germanium base layer and a silicon emitter layer is formed by means of Rapid Thermal Processing (RTP) to ensure enhanced component ... | 10/10/2006 |
| 7091056 | Method of manufacturing a semiconductor light emitting device, semiconductor light emitting device, method of manufacturing a semiconductor device, semiconductor device, method of manufacturing a device, and device When a semiconductor light emitting device or a semiconductor device is manufactured by growing nitride III–V compound semiconductor layers, which will form a light emitting device structure or a device structure, on a nitride III–V compound semiconductor substr... | 08/15/2006 |
| 7078353 | Indirect bonding with disappearance of bonding layer The invention provides a method of producing a structure of a thin layer of semiconductor material on a support substrate. The thin layer is obtained from a donor substrate and includes an upper layer of semiconductor material. The method includes forming on the upp... | 07/18/2006 |
| 7074685 | Method of fabrication SiGe heterojunction bipolar transistor A method of fabricating a semiconductor device includes a SiGe(C) heterojunction bipolar transistor using a non-selective epitaxial growth where an insulating layer is formed on a substrate and a layer structure including a conductive layer is provided on the insula... | 07/11/2006 |
| 7071039 | Manufacturing method of partial SOI wafer, semiconductor device using the partial SOI wafer and manufacturing method thereof A semiconductor device includes a first semiconductor region having a buried oxide layer formed therein, a second semiconductor region in which the buried oxide layer does not exist, a trench formed to such a depth as to reach at least the buried oxide layer in a bo... | 07/04/2006 |
| 7049240 | Formation method of SiGe HBT A method for forming a SiGe HBT, which combines a SEG and Non-SEG growth, is disclosed. The SiGe base layer is deposited by a Non-SEG method. Then, the first-emitter layer is developed directly upon the SiGe base layer that has a good interface quality between the b... | 05/23/2006 |
| 7037798 | Bipolar transistor structure with self-aligned raised extrinsic base and methods The invention includes methods of fabricating a bipolar transistor that adds a silicon germanium (SiGe) layer or a third insulator layer of, e.g., high pressure oxide (HIPOX), atop an emitter cap adjacent the intrinsic base prior to forming a link-up layer. This add... | 05/02/2006 |
| 7033901 | Buried power buss utilized as a ground strap for high current, high power semiconductor devices and a method for providing the same A method and system for providing a ground strap on a semiconductor device is disclosed. The method and system includes providing a substrate region and providing an epitaxial (EPI) layer over the substrate region. The method and system includes etching a plurality ... | 04/25/2006 |
| 6979884 | Bipolar transistor having self-aligned silicide and a self-aligned emitter contact border The present invention provides a bipolar transistor having a raised extrinsic base silicide and an emitter contact border that are self-aligned. The bipolar transistor of the present invention exhibit reduced parasitics as compared with bipolar transistors that do n... | 12/27/2005 |
| 6977204 | Method for forming contact plug having double doping distribution in semiconductor device The present invention provides a method for forming a contact plug in a semiconductor device capable of preventing an increase of contact resistance caused by a decrease in dopant concentration and suppressing diffusions of dopants implanted into the contact. The do... | 12/20/2005 |
| 6965132 | Polycrystalline silicon emitter having an accurately controlled critical dimension According to a disclosed embodiment, an etch stop layer is fabricated on top of a base. An amorphous layer is then formed on top of the etch stop layer. An opening is then etched in the amorphous layer and the etch stop layer. The opening is etched with an opening w... | 11/15/2005 |
| 6881650 | Method for forming SOI substrate A method for forming SOI substrates including a SOI layer containing germanium and a strained silicon layer disposed on the SOI layer, comprises forming a relaxed silicon-germanium layer on a first silicon substrate using an epitaxial growth method, and forming a po... | 04/19/2005 |
| 6855620 | Method for fabricating Group III nitride compound semiconductor substrates and semiconductor devices A GaN layer 31 is subjected to etching, so as to form an island-like structure having, for example, a dot, stripe, or grid shape, thereby providing a trench/mesa structure including mesas and trenches whose bottoms sink into the surface of a substrate base | 02/15/2005 |
| 6841457 | Use of hydrogen implantation to improve material properties of silicon-germanium-on-insulator material made by thermal diffusion A method of forming a relaxed SiGe-on-insulator substrate having enhanced relaxation, significantly lower defect density and improved surface quality is provided. The method includes forming a SiGe alloy layer on a surface of a first single crystal Si layer. The fir... | 01/11/2005 |
| 6818521 | Method of manufacturing a hetero-junction bipolar transistor with epitaxially grown multi-layer films and annealing at or below 600° C. This invention provides a method for manufacturing a hetero-junction bipolar transistor, in which a hole concentration of a base layer doped with carbon can be increased. The method comprises the following steps. 1) A sub-collector 30, a collector 50, ... | 11/16/2004 |
| 6784063 | Method for fabricating BiCMOS transistor The present invention discloses a method for fabricating a BiCMOS transistor, which improves the high frequency characteristics of a bipolar transistor by reducing base resistance and a parasitic capacitance between the base and collector. The method comprises the s... | 08/31/2004 |
