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| Number | Title | Issue Date |
| 8076211 | Fabricating bipolar junction select transistors for semiconductor memories A bipolar junction transistor may act as a select device for a semiconductor memory. The bipolar junction transistor may be formed of a stack of base and collector layers. Sets of parallel trenches are formed in a first direction down to the base and in a second dir... | 12/13/2011 |
| 7968417 | Method for integrating high voltage and high speed bipolar transistors on a substrate and related structure According to an exemplary embodiment, a method for integrating a high speed bipolar transistor in a high speed transistor region of a substrate with a high voltage transistor in a high voltage transistor region of the substrate includes forming a buried subcollector... | 06/28/2011 |
| 7456070 | Method of fabricating a bipolar transistor with high breakdown voltage collector A method of fabricating a transistor that includes a doped buried region within a semiconductor body. The doped buried region includes a portion having a first thickness and a second thickness, the first thickness being less than the second thickness. In one embodim... | 11/25/2008 |
| 7327012 | Bipolar Transistor Devices A method of forming bipolar transistors by using the same mask to form the collector region in a substrate of an opposite conductivity type as to form the base in the collector region. More specifically, impurities of a first conductivity type are introduced into a ... | 02/05/2008 |
| 7285469 | Bipolar method and structure having improved BVCEO/RCS trade-off made with depletable collector columns In accordance with the invention, there are various methods of making an integrated circuit comprising a bipolar transistor. According to an embodiment of the invention, the bipolar transistor can comprise a substrate, a collector comprising a plurality of alternati... | 10/23/2007 |
| 7271046 | Method of making a semiconductor device in which a bipolar transistor and a metal silicide layer are formed on a substrate A semiconductor device includes a bipolar transistor formed on a semiconductor substrate 1, in which a collector region 13 is formed on the semiconductor substrate 1; a first insulating layer 31 having a first opening 51 formed in ... | 09/18/2007 |
| 7226835 | Versatile system for optimizing current gain in bipolar transistor structures Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406 | 06/05/2007 |
| 7217628 | High performance integrated vertical transistors and method of making the same A complementary bipolar transistor is fabricated using an available portion of a silicon germanium (SiGe) low temperature epitaxial layer as the raised base region for a vertical NPN transistor, and another portion of the same SiGe LTE layer as a vertical PNP collec... | 05/15/2007 |
| 7206552 | Semiconductor switching device A semiconductor switching device includes two FETs with different device characteristics, a common input terminal, and two output terminals. The gate width of each FET is about 400 μm, and the maximum power required for the device operation is maintained by a lager... | 04/17/2007 |
| 7192838 | Method of producing complementary SiGe bipolar transistors Method of producing complementary SiGe bipolar transistors. In a method of producing complementary SiGe bipolar transistors, interface oxide layers (38, 58) for NPN and PNP emitters (44, 64), are separately formed and emitter polysilicon (40, 60... | 03/20/2007 |
| 7144789 | Method of fabricating complementary bipolar transistors with SiGe base regions In a method of fabricating complementary bipolar transistors with SiGe base regions the base regions of the NPN and PNP transistors are formed one after the other over two collector regions 20, 14 by epitaxial deposition of crystalline silicon-germanium layer... | 12/05/2006 |
| 7109567 | Semiconductor device and method of manufacturing such device The invention relates to a semiconductor device with a heterojunction bipolar, in particular npn, transistor with an emitter region (1), a base region (2), and a collector region (3), which are provided with respectively a first, a second, and a... | 09/19/2006 |
| 7092740 | High density information presentation using space-constrained display device A high-density information presentation is provided on a space-constrained display device by associating individual display indications with user-definable states. For example, using a portion of a space-constrained display of a mobile phone, pager personal digital ... | 08/15/2006 |
| 7071536 | Semiconductor device and manufacturing method thereof A high voltage semiconductor device having a high current gain hFE is formed with a collector region (20) of a first conduction type, an emitter region (40) of the first conduction type, and a base region (30) of a second conduction type opposit... | 07/04/2006 |
| 7060583 | Method for manufacturing a bipolar transistor having a polysilicon emitter In the inventive method for manufacturing a bipolar transistor having a polysilicon emitter, a collector region of a first conductivity type and, adjoining thereto, a basis region of a second conductivity type will be generated at first. At least one layer of an ins... | 06/13/2006 |
| 7052584 | Method of forming a capacitor A method of forming a capacitor having a capacitor dielectric layer comprising ABO3, where “A” is selected from the group consisting of Sn and Group IIA metal elements and mixtures thereof, where “B” is selected from the group consisting of Group ... | 05/30/2006 |
| 7037799 | Breakdown voltage adjustment for bipolar transistors Devices and methods are disclosed related to a bipolar transistor device and methods of fabrication. A top region is formed at a surface of and within a base region. The top region is formed by implanting a dopant of an opposite conductivity to that of the base regi... | 05/02/2006 |
| 7015085 | Super self-aligned collector device for mono-and hetero bipolar junction transistors and method of making same The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the ... | 03/21/2006 |
| 7001806 | Semiconductor structure with increased breakdown voltage and method for producing the semiconductor structure A semiconductor structure comprises a buried first semiconductor layer of a first doping type, a second semiconductor layer of the first doping type on the buried semiconductor layer, which is less doped than the buried first semiconductor layer, a semiconductor are... | 02/21/2006 |
| 6992338 | CMOS transistor spacers formed in a BiCMOS process According to an exemplary method in one embodiment, a transistor gate is fabricated on a substrate. Next, an etch stop layer may be deposited on the substrate. The etch stop layer may, for example, be TEOS silicon dioxide. Thereafter, a conformal layer is deposited ... | 01/31/2006 |
| 6984567 | Nonvolatile semiconductor memory device and manufacturing method thereof A nonvolatile semiconductor memory device having a memory cell comprising source/drain diffusion layer in p-well formed to a silicon substrate, a floating gate as a first gate, a control gate (word line) as a second gate, and a third gate, in which the floating gate... | 01/10/2006 |
| 6977426 | Semiconductor device including high speed transistors and high voltage transistors disposed on a single substrate In a semiconductor device comprising a first bipolar transistor and a second bipolar transistor having different voltages formed on a semiconductor substrate made by forming an epitaxial layer on a silicon substrate, in an upper part of the silicon substrate the fir... | 12/20/2005 |
| 6940149 | Structure and method of forming a bipolar transistor having a void between emitter and extrinsic base Structure and a method are provided for making a bipolar transistor, the bipolar transistor including a collector, an intrinsic base overlying the collector, an emitter overlying the intrinsic base, and an extrinsic base spaced from the emitter by a gap, the gap inc... | 09/06/2005 |
| 6930008 | Method of fabricating a complementary bipolar junction transistor A method of fabricating a complementary bipolar junction transistor includes forming a polycrystalline silicon layer on an NPN bipolar junction transistor region and a PNP bipolar junction transistor region, respectively implanting an N-type impurity and a P-type im... | 08/16/2005 |
| 6924535 | Semiconductor device with high and low breakdown voltage transistors A semiconductor device, having a high breakdown voltage transistor and a low breakdown voltage transistor in a common substrate with different driving voltages, includes a semiconductor substrate of a first conductivity type, a first triple well formed in the semico... | 08/02/2005 |
| 6888221 | BICMOS technology on SIMOX wafers A method and structure for a bipolar transistor comprising a patterned isolation region formed below an upper surface of a semiconductor substrate and a single crystal extrinsic base formed on an upper surface of the isolation region. The single crystal extrinsic ba... | 05/03/2005 |
| 6838348 | Integrated process for high voltage and high performance silicon-on-insulator bipolar devices High-voltage bipolar transistors (30, 60) in silicon-on-insulator (SOI) integrated circuits are disclosed. In one disclosed embodiment, an collector region (28) is formed in epitaxial silicon (24, 25) disposed over a buried insulator layer (2... | 01/04/2005 |
| 6806129 | Self-aligned process using indium gallium arsenide etching to form reentry feature in heterojunction bipolar transistors A method for forming a heterojunction bipolar transistor (HBT) includes forming an etch mask a top layer of the HBT to expose a portion of the emitter cap layer, and selectively etching the exposed portion of the emitter cap layer to (1) form a reentry feature and (... | 10/19/2004 |
| 6759303 | Complementary vertical bipolar junction transistors fabricated of silicon-on-sapphire utilizing wide base PNP transistors A method for fabricating complementary vertical bipolar junction transistors of silicon-on-sapphire in fewer steps than required for true complimentary vertical bipolar junction transistors is disclosed. Initially a thin layer of silicon is grown on a sapphire subst... | 07/06/2004 |
| 6740563 | Amorphizing ion implant method for forming polysilicon emitter bipolar transistor A method for fabricating a polysilicon emitter bipolar transistor employs a pair of ion implant methods. A first of the icon implant methods implants a portion of an intrinsic base region interposed between an extrinsic base region and a polysilicon emitter layer wi... | 05/25/2004 |
| RE38510 | Manufacturing process for a monolithic semiconductor device comprising at least one transistor of an integrated control circuit and one power transistor integrated on the same chip The device uses the horizontal insulating region and the buried layer as the power transistor base and emitter respectively. An epitaxial growth is interposed between the two diffusions needed to form the aforesaid regions and those needed to create the base and the... | 05/04/2004 |
| 6703685 | Super self-aligned collector device for mono-and hetero bipolar junction transistors The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is dispo... | 03/09/2004 |
| 6699741 | Single poly bipolar transistor and method that uses a selectively epitaxially grown highly-boron-doped silicon layer as a diffusion source for an extrinsic base region A high frequency bipolar transistor that has a silicon germanium intrinsic base region is formed in a semiconductor fabrication process that forms the extrinsic base regions after the intrinsic base region has been formed. The extrinsic base regions are e... | 03/02/2004 |
| 6683366 | Bipolar transistor and related structure According to one exemplary embodiment, a bipolar transistor, such as a heterojunction bipolar transistor ("HBT"), comprises a base having a top surface. The HBT further comprises a first inner spacer and a second inner spacer situated on the top surface o... | 01/27/2004 |
| 6656809 | Method to fabricate SiGe HBTs with controlled current gain and improved breakdown voltage characteristics A method of fabricating a SiGe heterojunction bipolar transistor (HBT) is provided which results in a SiGe HBT that has a controllable current gain and improved breakdown voltage. The SiGe HBT having these characteristics is fabricated by forming an in-si... | 12/02/2003 |
| 6645820 | Polycrystalline silicon diode string for ESD protection of different power supply connections An ESD protection circuit protects integrated circuits having multiple power supply voltage sources from damage when an ESD event causes excessive differential voltages between the multiple separate power supply voltage sources. The ESD protection circuit... | 11/11/2003 |
| 6566217 | Manufacturing process for semiconductor device A manufacturing process for a semiconductor device including a semiconductor memory region and a peripheral circuit region including bipolar transistors, in which a plurality of bipolar transistors with characteristics different from each other are effect... | 05/20/2003 |
| 6521972 | RF power transistor having low parasitic impedance input feed structure An RF microwave power transistor has an input/output feed structure which functions as a low impedance microstrip line by providing a ground plane in close proximity to the feed structure on one surface of a semiconductor body. A second ground plane can b... | 02/18/2003 |
| 6518139 | Power semiconductor device structure with vertical PNP transistor A power semiconductor device structure formed in a chip of semiconductor material includes an N-type substrate and an N-type epitaxial layer. The structure comprises a P-type insulation region which forms a pocket in which control circuitry is formed, and... | 02/11/2003 |
| 6472286 | Bipolar ESD protection structure The invention describes the fabrication and structure of an ESD protection device for integrated circuit semiconductor devices with improved ESD protection and resiliency. A vertical bipolar npn transistor forms the basis of the protection device. To hand... | 10/29/2002 |
