Class 438/339 - Self-aligned

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process for making a lateral bipolar transistor wherein
No. of patents: 90
Last issue date: 06/07/2011

«First «Previous1 2 3 Next»Last»

Number	Title	Issue Date
7955939	Method for producing a high capacitance cathode by annealing a metallic foil in a nitrogen environment The present invention is a method for the production of a high capacitance foil for use as a cathode in an electrolytic capacitor by forming a nitride layer on at least one surface of the foil by annealing the foil at an elevated temperature in the presence of nitro...	06/07/2011
7297607	Device and method of performing a seasoning process for a semiconductor device manufacturing apparatus A method of performing a seasoning process for a semiconductor device processing apparatus is provided by the present invention. The method includes: forming a material layer on a test wafer; coating a photoresist on the material layer; patterning the photoresist so...	11/20/2007
7285454	Bipolar transistors with low base resistance for CMOS integrated circuits Complementary metal-oxide-semiconductor (CMOS) integrated circuits with bipolar transistors and methods for fabrication are provided. A bipolar transistor may have a lightly-doped base region. To reduce the resistance associated with making electrical contact to the...	10/23/2007
7282418	Method for fabricating a self-aligned bipolar transistor without spacers According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a sacrificial post situated on the top surface of the base. The bipolar transistor also comprises a conformal layer situated o...	10/16/2007
7276419	Semiconductor device and method for forming the same A semiconductor device may include first, second, and third semiconductor layers. The first and third layers may have a first dopant type, and the second layer may have a second dopant type. A first region within the third semiconductor layer may have the second dop...	10/02/2007
7179537	Spin-on glass composition and method of forming silicon oxide layer in semiconductor manufacturing process using the same A spin-on glass (SOG) composition and a method of forming a silicon oxide layer utilizing the SOG composition are disclosed. The method includes coating on a semiconductor substrate having a surface discontinuity, an SOG composition containing perhydropolysilazane h...	02/20/2007
7067383	Method of making bipolar transistors and resulting product A method of forming bipolar transistors by using the same mask to form the collector region in a substrate of an opposite conductivity type as to form the base in the collector region. More specifically, impurities of a first conductivity type are introduced into a ...	06/27/2006
7038298	High fand fbipolar transistor and method of making same A high fT and fmax bipolar transistor (100) includes an emitter (104), a base (120), and a collector (116). The emitter has a lower portion (108) and an upper portion (112) that extends beyond the lower...	05/02/2006
7037814	Single mask control of doping levels In an integrated circuit, dopant concentration levels are adjusted by making use of a perforated mask. Doping levels for different regions across an integrated circuit can be differently defined by making use of varying size and spacings to the perforations in the m...	05/02/2006
6972472	Quasi self-aligned single polysilicon bipolar active device with intentional emitter window undercut An emitter stack for a quasi-self-aligned bipolar (NPN or PNP) transistor is formed where two layers over the emitter of a silicon substrate are windowed in a manner to under cut the top layer thereby exposing the substrate material. The emitter polysilicon structur...	12/06/2005
6946720	Bipolar transistor for an integrated circuit having variable value emitter ballast resistors An integrated circuit including a bipolar transistor with improved forward second breakdown is disclosed. In one embodiment, the bipolar transistor includes a base, a collector, a plurality of emitter sections coupled to a common emitter and a ballast emitter for ea...	09/20/2005
6908810	Method of preventing threshold voltage of MOS transistor from being decreased by shallow trench isolation formation A method of preventing decreasing threshold voltage of a MOS transistor by formation of shallow trench isolation. Shallow trenches are formed to isolate first active regions and second active regions. The first active regions are located within a core circuit region...	06/21/2005
6844225	Self-aligned mask formed utilizing differential oxidation rates of materials A self-aligned oxide mask is formed utilizing differential oxidation rates of different materials. The self-aligned oxide mask is formed on a CVD grown base NPN base layer which compromises single crystal Si (or Si/SiGe) at active area and polycrystal Si (or Si/SiGe...	01/18/2005
6815801	Vertical bipolar transistor and a method of manufacture therefor including two epitaxial layers and a buried layer The present invention provides a vertical bipolar transistor 110, a method of manufacture therefor, and an integrated circuit including the same. The vertical bipolar transistor 110 may include, in one embodiment, a second epitaxial layer 140 lo...	11/09/2004
6809353	Method for fabricating a self-aligned bipolar transistor with planarizing layer and related structure According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises first and second link spacers situated on the top surface of the base. The bipolar transistor further comprises a sacrificial ...	10/26/2004
6764893	Method for reducing a parasitic capacitance of a semiconductive memory cell using metal mask for sidewall formation The present invention provides a method for reducing loading capacitance. The inventive method includes the steps of: forming a plurality of patterns on a substrate, wherein the patterns are formed by stacking and patterning a first conductive layer, a silicon nitri...	07/20/2004
6713361	Method of manufacturing a bipolar junction transistor including undercutting regions adjacent to the emitter region to enlarge the emitter region According to one embodiment of the invention, a method for manufacturing bipolar junction transistors includes disposing a first oxide layer between a semiconductor substrate and a base polysilicon layer, forming a dielectric layer outwardly from the base polysilico...	03/30/2004
6699741	Single poly bipolar transistor and method that uses a selectively epitaxially grown highly-boron-doped silicon layer as a diffusion source for an extrinsic base region A high frequency bipolar transistor that has a silicon germanium intrinsic base region is formed in a semiconductor fabrication process that forms the extrinsic base regions after the intrinsic base region has been formed. The extrinsic base regions are e...	03/02/2004
6686250	Method of forming self-aligned bipolar transistor A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has an emitter region characterized by a y-shaped structure formed from bilayer polysilicon. The bilayer polysilicon includes a first polysilicon emit...	02/03/2004
6656810	Semiconductor device capable of reducing dispersion in electrical characteristics and operating at high speed and method for fabricating the same There is provided a semiconductor device capable of reducing dispersion in electrical characteristics, preventing occurrence of bridge shortcircuit in a silicide process and operating at high operating speed and method for fabricating the same. In a SOI s...	12/02/2003
6611044	Lateral bipolar transistor and method of making same A lateral bipolar transistor for an intergrated circuit is provided that maintains a high current gain and high frequency capability without sacrificing high Early voltage. More particularly, a lateral bipolar transistor is formed on an integrated circuit...	08/26/2003
6436779	Semiconductor device having a plurality of resistive paths A semiconductor device has first and second opposed major surfaces (10a and 10b). A semiconductor first region (11) is provided between second (12 or 120) and third (14) regions such that the second region (12 or 120) forms a rectifying junction (13 or 13...	08/20/2002
6359307	Method for forming self-aligned contacts and interconnection lines using dual damascene techniques The present invention further provides a method for forming self-aligned contacts using a dual damascene techniques that reduces the number of process steps and results in a reduction in cycle time, cost and yield loss. In a preferred embodiment, a method...	03/19/2002
6255184	Fabrication process for a three dimensional trench emitter bipolar transistor A process for fabricating a bipolar junction transistor, featuring an N type, polysilicon emitter structure, located in an emitter trench, and featuring a narrow width. P type base region, located directly underlying an N type, emitter region, which is fo...	07/03/2001
6204161	Self aligned contact pad in a semiconductor device and method for forming the same Self-aligned contact pads in a semiconductor device and a method for forming the same are provided. These self-aligned contact pads can increase the upper surface of the contact pads to increase alignment margins. Portions of the gate mask are undercut, i...	03/20/2001
6124217	In-situ SiON deposition/bake/TEOS deposition process for reduction of defects in interlevel dielectric for integrated circuit interconnects An interlevel dielectric including a tetraethyl orthosilicate (TEOS) oxide and a silicon oxynitride (SiON) etch stop layer is formed for use in integrated circuit fabrication. A SiON layer is deposited onto a semiconductor substrate which may include tran...	09/26/2000
6114743	Well isolation bipolar transistor The present invention relates to an integrated circuit including a lateral well isolation bipolar transistor. A first portion of the upper internal periphery of the insulating well is hollowed and filled with polysilicon having the same conductivity type ...	09/05/2000
5846858	SOI-BiCMOS method In a manufacturing method for lateral bipolar transistors on an SOI substrate, a ridge-shaped gate electrode (8/9) is applied onto a mesa (3) provided with a basic doping and is covered surface-wide with a TEOS layer (10) that has vertical portions functi...	12/08/1998
5789285	Manufacturing method for BIMOS In a BiMOS semiconductor device, emitter and base electrodes formed by polycrystalline Si of a bipolar transistor are isolated from each other by way of a sidewall and an insulator layer. As this insulator layer acts as an offset during the formation of t...	08/04/1998
5666001	Transistor wherein the base area is covered with an insulating layer which is overlaid with a conductive film that might be polysilicon crystal or aluminum In production of a Bi-CMOS semiconductor device, when forming a lateral PNP transistor in a bipolar section, an oxide film is deposited on this base area to prevent etching damages such as those in forming an LDD spacer for a MOS section, thus degradation...	09/09/1997
5624856	Method for forming a lateral bipolar transistor A lateral bipolar transistor comprising a self-aligned polysilicon base contact, and polysilicon emitter and collector contacts is provided. The self-aligned base contact significantly reduces the base width and therefore the base resistance compared with...	04/29/1997
5610087	Method for fabricating narrow base width lateral bipolar junction transistor, on SOI layer A process has been developed in which narrow base width, lateral bipolar junction transistors, and short channel length MOSFET devices, can be simultaneously fabricated, in a silicon on insulator layer. The narrow base width is defined by the width of an ...	03/11/1997
5571731	Procedure for the manufacture of bipolar transistors without epitaxy and with fully implanted base and collector regions which are self-positioning relative to each other A method of fabricating a semiconductor device. A series of layers is deposited on a semiconductor substrate of a first conductivity type to form a shielding arrangement, including an upper part and a lower part, to provide a shield against accelerated io...	11/05/1996
5567631	Method of forming gate spacer to control the base width of a lateral bipolar junction transistor using SOI technology A process has been developed in which narrow base width, lateral bipolar junction transistors, and narrow channel length MOSFET devices, can be simultaneously fabricated, using a silicon on insulator approach. Insulator sidewall spacer and gate processing...	10/22/1996
5486481	Method for forming a lateral bipolar transistor A lateral bipolar transistor structure (10) formed in a laterally isolated semiconductor device tub (22) of a first conductivity type is provided. First and second trenches are etched in the device tub and filled with doped polysilicon of a second conduct...	01/23/1996
5455188	Process for fabricating a lateral bipolar junction transistor A process for fabricating lateral bipolar junction transistor semiconductor device. Base and emitter regions are precisely aligned. The resulting lateral width of the base region of the transistor device is able be precisely controlled. A heavily-doped im...	10/03/1995
5449627	Lateral bipolar transistor and FET compatible process for making it A lateral bipolar transistor and method of making the transistor are disclosed. The device is made by etching a trench around a central region of a semiconductor body. An emitter is buried beneath the surface of this central area and contact to it is made...	09/12/1995
5444004	CMOS process compatible self-alignment lateral bipolar junction transistor A self aligned lateral BJT is disclosed which has a lightly doped first region of a first conductivity type, e.g., P-type. A heavily doped polysilicon region, of a second conductivity type, e.g., N-type, is provided on a portion of a surface of the first ...	08/22/1995
5416031	Method of producing Bi-CMOS transistors In production of a Bi-CMOS semiconductor device, when forming a lateral PNP transistor in a bipolar section, an oxide film is deposited on this base area to prevent etching damages such as those in forming an LDD spacer for a MOS section, thus degradation...	05/16/1995
5407843	Method for manufacturing lateral bipolar transistors Method for manufacturing lateral bipolar transistors on a SOI substrate, whereby a basic doping for the conductivity type of emitter and collector is produced in the silicon layer of this SOI substrate, insulation regions are produced outside the region p...	04/18/1995

«First «Previous1 2 3 Next»Last»

PatentStorm

Quotables

PatentStorm News

Class 438/339 - Self-aligned