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| Number | Title | Issue Date |
| 8183120 | Method of making bipolar FinFET technology One or more embodiments relate to a method, comprising forming an implant on a substrate surface; selectively etching the wafer surface to form an elongated fin including portion of the implant; forming collector/emitter regions adjacent opposing ends of the fin; an... | 05/22/2012 |
| 8043924 | Methods of forming phase-change memory units, and methods of manufacturing phase-change memory devices using the same In a method of forming a phase-change memory unit, a conductive layer is formed on a substrate having a trench. The conductive layer is planarized until the substrate is exposed to form a first electrode. A spacer partially covering the first electrode is formed. A ... | 10/25/2011 |
| 7329583 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 02/12/2008 |
| 7279378 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/09/2007 |
| 7276431 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/02/2007 |
| 7208382 | Semiconductor device with high conductivity region using shallow trench A method and structure is provided for an integrated circuit with a semiconductor substrate having an opening provided therein. A doped high conductivity region is formed from doped material in the opening and a diffused dopant region proximate the doped material in... | 04/24/2007 |
| 7153542 | Assembly line processing method An apparatus for sequential processing of a workpiece comprises an assembly line processing system. The apparatus comprises multiple workpieces moving in an assembly line fashion under multiple process stations. The multiple process stations provide different proces... | 12/26/2006 |
| 7151035 | Semiconductor device and manufacturing method thereof A sidewall-insulation film 9 is provided on a side surface of a first opening portion 8a formed in a base extraction electrode 5B of a hetero-junction bipolar transistor, and a portion of the sidewall-insulation film 9 extends so a... | 12/19/2006 |
| 7118982 | Emitter and method of making An emitter includes an electron source and a cathode. The cathode has an emissive surface. The emitter further includes a continuous anisotropic conductivity layer disposed between the electron source and the emissive surface of the cathode. The anisotropic conducti... | 10/10/2006 |
| 7087925 | Semiconductor device having reduced capacitance to substrate and method In one embodiment, a matrix of free-standing semiconductor shapes are oxidized to form a low capacitance isolation tub. The adjacent rows of shapes in the matrix are offset with respect to each to minimize air gap and void formation during tub formation. In a furthe... | 08/08/2006 |
| 7067874 | Semiconductor device including trench with at least one of an edge of an opening and a bottom surface being round A semiconductor device that includes an insulating substrate, a plurality of semiconductor layers arranged to be isolated from one another on the insulating substrate, and a semiconductor element independently provided on the semiconductor layers. Further, a trench ... | 06/27/2006 |
| 7045880 | Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the direction. Advantageously, improvements in hole carrier mobility of approxim... | 05/16/2006 |
| 7045436 | Method to engineer the inverse narrow width effect (INWE) in CMOS technology using shallow trench isolation (STI) A method (200) of forming an isolation structure is disclosed, and includes forming an isolation trench in a semiconductor body (214) associated with an isolation region, and filling a bottom portion of the isolation trench with an implant masking mate... | 05/16/2006 |
| 7015086 | Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology A process for forming an isolation region comprised of shallow trench-deep trench configuration, wherein a smooth top surface topography is obtained for the isolation region and for adjacent active device regions in the semiconductor substrate, has been developed. T... | 03/21/2006 |
| 7001825 | Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same In some embodiments, a circuit structure comprises a semiconductor substrate, an opening passing through the substrate between a first side of the substrate and a second side of the substrate, and a plurality of conductive layers in the opening. In some embodiments,... | 02/21/2006 |
| 6894362 | Method and apparatus for a self-aligned heterojunction bipolar transistor using dielectric assisted metal liftoff process Disclosed is a manufacturing method to fabricate Heterojunction Bipolar Transistors (HBTs) that enables self-alignment of emitter and base metal contact layers with precise sub-micron spacing using a dielectric-assisted metal lift-off process. Such an HBT process re... | 05/17/2005 |
| 6787404 | Method of forming double-gated silicon-on-insulator (SOI) transistors with reduced gate to source-drain overlap capacitance A method of forming a double-gated transistor comprising the following sequential steps. A substrate having an SOI structure formed thereover is provided. The SOI structure including a lower SOI oxide layer and an upper SOI silicon layer. The SOI silicon layer is pa... | 09/07/2004 |
| 6656810 | Semiconductor device capable of reducing dispersion in electrical characteristics and operating at high speed and method for fabricating the same There is provided a semiconductor device capable of reducing dispersion in electrical characteristics, preventing occurrence of bridge shortcircuit in a silicide process and operating at high operating speed and method for fabricating the same. In a SOI s... | 12/02/2003 |
| 6436780 | Semiconductor device A number of npn and pnp bipolar transistors are formed in a single chip of silicon, so that some of the transistors have a greater frequency response than others The higher frequency transistors have their emitters located closer to the collectors, by pos... | 08/20/2002 |
| 6368946 | Manufacture of a semiconductor device with an epitaxial semiconductor zone A method of manufacturing a semiconductor device with an epitaxial semiconductor zone, whereby a first layer of insulating material, a first layer of non-monocrystalline silicon, and a second layer of insulating material are provided in that order on a su... | 04/09/2002 |
| 6346485 | Semiconductor wafer processing method and semiconductor wafers produced by the same A method of processing a semiconductor wafer sliced from a monocrystalline ingot comprises at least the steps of chamfering, lapping, etching, mirror-polishing, and cleaning. In the etching step, alkali etching is first performed and then acid etching, pr... | 02/12/2002 |
| 6340612 | Method of fabricating body contacted and backgated transistors A circuit and method for an improved inverter is provided. The present invention capitalizes on a switched source impedance to prevent subthreshold leakage current at standby in low voltage CMOS circuits. The switched source impedance is provided by body ... | 01/22/2002 |
| 6337251 | Method of manufacturing semiconductor device with no parasitic barrier In a method of manufacturing a semiconductor device, a first insulating film is formed on a semiconductor substrate, a first conductive film is formed on the first insulating film, and a second insulating film is formed on the first conductive film. An op... | 01/08/2002 |
| 6255184 | Fabrication process for a three dimensional trench emitter bipolar transistor A process for fabricating a bipolar junction transistor, featuring an N type, polysilicon emitter structure, located in an emitter trench, and featuring a narrow width. P type base region, located directly underlying an N type, emitter region, which is fo... | 07/03/2001 |
| 6248639 | Electrostatic discharge protection circuit and transistor A circuit protects against electrostatic discharge and includes a pad which receives an external signal source. The transistor of the present invention is connected to the circuit to be protected and includes a semiconductor body of a first conductivity t... | 06/19/2001 |
| 6245615 | Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the direction. Advantageously, improvements in hole carrier mobility ... | 06/12/2001 |
| 6136701 | Contact structure for semiconductor device and the manufacturing method thereof A contact structure of a semiconductor device includes an impurity-doped region formed in the semiconductor substrate, a trench having a groove in the semiconductor substrate, with the groove being in contact with at least one side face of the impurity-do... | 10/24/2000 |
| 6110799 | Trench contact process A trench process for establishing a contact for a semiconductor device with trenches such as the trench and planar MOSFETs (UMOS), trench and planar IGBTs and trench MCTs which reduces the number of masks and eliminates the need for lateral diffusion into... | 08/29/2000 |
| 5786258 | Method of making an SOI transistor A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by... | 07/28/1998 |
| 5580797 | Method of making SOI Transistor A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by... | 12/03/1996 |
| 5455188 | Process for fabricating a lateral bipolar junction transistor A process for fabricating lateral bipolar junction transistor semiconductor device. Base and emitter regions are precisely aligned. The resulting lateral width of the base region of the transistor device is able be precisely controlled. A heavily-doped im... | 10/03/1995 |
| 5449627 | Lateral bipolar transistor and FET compatible process for making it A lateral bipolar transistor and method of making the transistor are disclosed. The device is made by etching a trench around a central region of a semiconductor body. An emitter is buried beneath the surface of this central area and contact to it is made... | 09/12/1995 |
| 5371022 | Method of forming a novel vertical-gate CMOS compatible lateral bipolar transistor A transistor with silicon on insulator (SOI) intrinsic base and a collector each formed by a low temperature epitaxial process and each orientated vertically with respect to the (SOI) substrate. The base width can be as narrow as in a conventional vertica... | 12/06/1994 |
| 5352624 | SOI type semiconductor device and manufacturing method therefor A lateral bipolar transistor including a transistor forming region provided on an insulating substrate; a first impurity diffusing region provided on the insulating substrate on one side of the transistor forming region; an emitter region formed in a firs... | 10/04/1994 |
| 5273913 | High performance lateral PNP transistor with buried base contact A high performance PNP lateral bipolar transistor is described, incorporating at least two trenches extending from the upper P- surface of a semiconductor substrate almost to a buried N+ layer. The floor of one trench is heavily N-do... | 12/28/1993 |
| 5234845 | Method of manufacturing semiconductor IC using selective poly and EPI silicon growth Herein disclosed is an improved bipolar transistor manufacturing method which adopts an EBT (Epitaxial Base Transistor) structure using an SPESG (Selective Poly-and-Epitaxial-Silicon Growth) technique. Specifically, the method of manufacturing a bipolar t... | 08/10/1993 |
| 5198376 | Method of forming high performance lateral PNP transistor with buried base contact A high performance PNP lateral bipolar transistor is described, incorporating at least two trenches extending from the upper P- surface of a semiconductor substrate almost to a buried N+ layer. The floor of one trench is heavily N-d... | 03/30/1993 |
| 5065210 | Lateral transistor structure for bipolar semiconductor integrated circuits A lateral transistor with a fine structure includes a semiconductor substrate of one conductivity type on which a mesa-shaped projection of opposite conductivity type is provided. The projection has side walls opposed to each other and serves as a collect... | 11/12/1991 |
| 5061645 | Method of manufacturing a bipolar transistor A method of manufacturing a bipolar transistor semiconductor device wherein the active regions of a transistor are formed in an opening provided in an insulating film, electrodes are led out by a polycrystalline silicon film formed on the insulating film,... | 10/29/1991 |
| 5047823 | Circuit structure having a lateral bipolar transistor and its method of manufacture A circuit structure contains at least one bipolar transistor whose emitter is fashioned as a part of a doped silicon layer grown on a substrate. The doped silicon layer comprises a sidewall extending parallel to its surface normal, the sidewall being cove... | 09/10/1991 |
