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| Number | Title | Issue Date |
| 8114750 | Lateral diffusion field effect transistor with drain region self-aligned to gate electrode A disposable structure displaced from an edge of a gate electrode and a drain region aligned to the disposable structure is formed. Thus, the drain region is self-aligned to the edge of the gate electrode. The disposable structure may be a disposable spacer, or alte... | 02/14/2012 |
| 7932156 | Bipolar transistor having a second, base-comprising region consisting of a first layer, a second, constrictive, layer, and a third layer The invention relates to a semiconductor device (10) with a substrate (12) and a semiconductor body (11) of silicon comprising a bipolar transistor with an emitter region, a base region and a collector region (1,2,3) first conductivity ty... | 04/26/2011 |
| 7446012 | Lateral PNP transistor and the method of manufacturing the same The present invention relates to a lateral PNP transistor and the method of manufacturing the same. The medium doping N-type base area and the light doping P− collector area were first introduced in the structure before the formation of P+ do... | 11/04/2008 |
| 7432169 | Method for manufacturing semiconductor device An excessive etch in the conventional manufacturing process causes a roughened surface of a contact bottom, resulting in an increased variation in characteristics of semiconductor devices. A bipolar transistor having a collector region 4 provided in a bottom ... | 10/07/2008 |
| 7352042 | Radiation-emitting semiconductor device and method of manufacturing such a device The invention relates to a radiation-emitting semiconductor device (10) with a semiconductor body (1) and a substrate (2), wherein the semiconductor body (1) comprises a vertical bipolar transistor with an emitter region (3), a bas... | 04/01/2008 |
| 7332788 | Semiconductor power device with charge compensation structure and monolithic integrated circuit, and method for fabricating it The invention relates to a semiconductor power device with charge compensation structure and monolithic integrated circuit, and method for fabricating it. In the case of this semiconductor power device, zones (6) in charge compensation cells (27) that ... | 02/19/2008 |
| 7320922 | Integrated circuit and method for manufacturing an integrated circuit on a semiconductor chip An integrated circuit on a semiconductor chip is provided with a first bipolar transistor and a second bipolar transistor. The first bipolar transistor has a first collector region of a first conductivity type, grown by at least one epitaxial layer, and the second b... | 01/22/2008 |
| 7309883 | Semiconductor device capable of preventing current flow caused by latch-up and method of forming the same A semiconductor device includes first, second, and third wells. The first well is connected to a pad to which an external pin is connected and includes a first-type diffusion region that receives a well bias voltage. The second well is adjacent to the first well, an... | 12/18/2007 |
| 7208332 | Methods for preserving strained semiconductor substrate layers during CMOS processing Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be forme... | 04/24/2007 |
| 7202121 | Methods for preserving strained semiconductor substrate layers during CMOS processing Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be forme... | 04/10/2007 |
| 7169660 | Lithography-independent fabrication of small openings for forming vertical mos transistor A method for formation of openings in semiconducting devices not limited by constraints of photolithography include forming a first dielectric layer over a semiconducting substrate, depositing a polysilicon layer over the first dielectric layer, forming a second die... | 01/30/2007 |
| 7098113 | Method and system for providing a power lateral PNP transistor using a buried power buss A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer; an emitter region between the first and second collector regions. Therefore slots are placed in each of the regions. Accor... | 08/29/2006 |
| 7071014 | Methods for preserving strained semiconductor substrate layers during CMOS processing Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be forme... | 07/04/2006 |
| 6949439 | Semiconductor power component and a method of producing same A semiconductor power component and a method for producing a semiconductor power component, in particular a vertical NPT-IGBT for ignition applications with a breakdown voltage of less than approx. 1000 V. The semiconductor power component includes a wafer substrate... | 09/27/2005 |
| 6919168 | Masking methods and etching sequences for patterning electrodes of high density RAM capacitors A method of etching a noble metal electrode layer disposed on a substrate to produce a semiconductor device including a plurality of electrodes separated by a distance equal to or less than about 0.35 μm and having a noble metal profile equal to or greater than abo... | 07/19/2005 |
| 6890826 | Method of making bipolar transistor with integrated base contact and field plate A method of manufacturing a bipolar junction transistor results in an integrated polysilicon base contact and field plate element minimally spaced from a polysilicon emitter contact by using a single mask to define respective openings for these elements. In particul... | 05/10/2005 |
| 6835629 | Power integrated circuit with vertical current flow and related manufacturing process Integrated circuit including a power component with vertical current flow and at least one low or medium voltage component, the at least one low or medium voltage component formed in a first semiconductor layer separated from a second semiconductor layer by an insul... | 12/28/2004 |
| 6818521 | Method of manufacturing a hetero-junction bipolar transistor with epitaxially grown multi-layer films and annealing at or below 600° C. This invention provides a method for manufacturing a hetero-junction bipolar transistor, in which a hole concentration of a base layer doped with carbon can be increased. The method comprises the following steps. 1) A sub-collector 30, a collector 50, ... | 11/16/2004 |
| 6790722 | Logic SOI structure, process and application for vertical bipolar transistor A method and structure for forming an emitter in a vertical bipolar transistor includes providing a substrate having a collector layer and a base layer over the collector layer, forming a patterning mask over the collector layer, and filling openings in the mask wit... | 09/14/2004 |
| 6720622 | SCR-ESD structures with shallow trench isolation A novel device structure and process are described for an SCR ESD protection device used with shallow trench isolation structures. The invention incorporates an SCR device with all SCR elements essentially contained within the sane active area without STI elements b... | 04/13/2004 |
| 6713361 | Method of manufacturing a bipolar junction transistor including undercutting regions adjacent to the emitter region to enlarge the emitter region According to one embodiment of the invention, a method for manufacturing bipolar junction transistors includes disposing a first oxide layer between a semiconductor substrate and a base polysilicon layer, forming a dielectric layer outwardly from the base polysilico... | 03/30/2004 |
| 6693013 | Semiconductor transistor using L-shaped spacer and method of fabricating the same The present invention provides a semiconductor transistor using an L-shaped spacer and a method of fabricating the same. The semiconductor transistor includes a gate pattern formed on a semiconductor substrate and an L-shaped third spacer formed beside th... | 02/17/2004 |
| 6692982 | Optical semiconductor integrated circuit device and manufacturing method for the same In an optical semiconductor integrated circuit device in which a vertical pnp transistor and a photodiode are formed, the preferred embodiments of the present invention eliminates difficulty in performance improvement of the two elements. In an illustrati... | 02/17/2004 |
| 6518139 | Power semiconductor device structure with vertical PNP transistor A power semiconductor device structure formed in a chip of semiconductor material includes an N-type substrate and an N-type epitaxial layer. The structure comprises a P-type insulation region which forms a pocket in which control circuitry is formed, and... | 02/11/2003 |
| 6448125 | Electronic power device integrated on a semiconductor material and related manufacturing process An electronic power device is integrated on a substrate of semiconductor material having a first conductivity type, on which an epitaxial layer of the same type of conductivity is grown. The power device comprises a power stage PT and a control stage CT, ... | 09/10/2002 |
| 6333237 | Method for manufacturing a semiconductor device A method for manufacturing a semiconductor device separately forms two collector regions, two base extension regions, two base regions, and two collector extension regions on a first bipolar transistor forming region and a second bipolar transistor formin... | 12/25/2001 |
| 6291303 | Method for manufacturing a bipolar junction device A method of forming an improved bipolar junction device structure. By forming a well region around the emitter terminal, the area of distribution of ions within the emitter terminal of a vertical bipolar junction transistor is enlarged. Furthermore, by fo... | 09/18/2001 |
| 6284615 | Method and apparatus for the selective doping of semiconductor material by ion implantation The method comprises forming an implantation screening layer of predetermined thickness on the wafer, forming, in the screening layer, a first rectilinear, elongate opening having a first width, and at least a second rectilinear, elongate opening substant... | 09/04/2001 |
| 6156604 | Method for making an open bit line memory cell with a vertical transistor and trench plate trench capacitor A circuit and method for a memory cell with a vertical transistor and a trench capacitor. The cell includes an access transistor that is formed in a pillar of a single crystal semiconductor material. The transistor has vertically aligned first and second ... | 12/05/2000 |
| 6150224 | Method of manufacturing a semiconductor device with a bipolar transistor The invention relates to the manufacture of a so-called differential bipolar transistor comprising a base (1A), an emitter (2) and a collector (3), the base (1A) being formed by applying a doped semiconducting layer (1) which locally borders on a monocrys... | 11/21/2000 |
| 6136635 | Method for forming a bipolar-based active pixel sensor cell with poly contact and increased capacitive coupling to the base region The dynamic range is increased and the noise level is reduced in a bipolar-based active pixel sensor cell with a capacitively coupled base region by forming the capacitor over a portion of the base region and the field oxide region of the cell. In additio... | 10/24/2000 |
| 6077753 | Method for manufacturing vertical bipolar transistor having a field shield between an interconnecting layer and the field oxide The present invention relates to a vertical bipolar power transistor primarily intended for radio frequency applications and to a method for manufacturing the bipolar power transistor. The power transistor comprises a substrate (13), a collector layer (15... | 06/20/2000 |
| 5914180 | Magnetic recording medium A magnetic recording medium having a thin magnetic metal film formed by vapor deposition under an atmosphere of an introduced oxygen gas. The thickness of the surface oxide film having the degree of oxidation of 50% or higher is maintained so as to be not... | 06/22/1999 |
| 5846866 | Drain extension regions in low voltage lateral DMOS devices Disclosed are MOSFET devices in which a region extends from the drain and is, self-aligned with the gate. The region has a lower dopant concentration than the drain. The presence of the extension region substantially enhances breakdown voltage while not a... | 12/08/1998 |
| 5679587 | Method of fabricating an integrated circuit with vertical bipolar power transistors and isolated lateral bipolar control transistors An integrated circuit containing both power and small-signal NPN bipolar devices. The small-signal devices use lateral current flow, and are completely surrounded (laterally and vertically) by an N-type well region. The N-type well region itself is comple... | 10/21/1997 |
| 5591665 | Process for producing a semiconductor structure including a plurality of vertical semiconductor devices and at least one lateral semiconductor device integrated in a semiconductor body A method is provided for forming a semiconductor device including a semiconductor body having a first surface and a second surface located opposite the first surface, with a plurality of vertical semiconductor components extending between the first and se... | 01/07/1997 |
| 5198375 | Method for forming a bipolar transistor structure A vertical bipolar transistor (10) and a lateral bipolar transistor (11) are formed wherein both transistors (10 and 11) have a substrate (12). A dielectric layer (22) is formed overlying the substrate (12), and a conductive layer (24) is formed overlying... | 03/30/1993 |
| 4956305 | Process for fabricating an integrated circuit The invention relates to a pnp lateral transistor comprised of two regions of p-type conductivity which are incorporated into the surface of a semiconductor area of n-type conductivity and constitute the emitter and collector regions. The portion of the s... | 09/11/1990 |
| 4717678 | Method of forming self-aligned P contact Disclosed is a process for forming self-aligned low resistance ohmic contact to a P doped region (e.g., base of an NPN device) in conjunction with forming similar contact to a (highly) N doped region (e.g., emitter of NPN). After forming a P doped region ... | 01/05/1988 |
| 4624046 | Oxide isolation process for standard RAM/PROM and lateral PNP cell RAM An oxide-isolated RAM and PROM process is disclosed wherein a RAM circuit includes a lateral PNP transistor formed in the same island of silicon material as a vertical NPN device and further wherein contact is made to the base of the lateral PNP and to th... | 11/25/1986 |
