Quotables
"The abolishment of pain in surgery is a chimera. It is absurd to go on seeking it...knife and pain are two words in surgery that must forever be associated in the consciousness of the patient."
Dr. Alfred Velpeau, French surgeon ; 1839
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8129249 | Integrated transistor, particularly for voltages and method for the production thereof Integrated transistor and method for the production is disclosed. An explanation is given of, inter alia, a transistor having an electrically insulating isolating trench extending from a main area in the direction of a connection region remote from the main area. Mo... | 03/06/2012 |
| 8021952 | Integrated transistor, particularly for voltages and method for the production thereof Integrated transistor and method for the production is disclosed. An explanation is given of, inter alia, a transistor having an electrically insulating isolating trench extending from a main area in the direction of a connection region remote from the main area. Mo... | 09/20/2011 |
| 7851320 | Mesostructured aluminosilicate material A mesostructured aluminosilicate material is described, constituted by at least two spherical elementary particles, each of said spherical particles being constituted by a matrix based on silicon oxide and aluminum oxide, having a pore size in the range 1.5 to 30 nm... | 12/14/2010 |
| 7572707 | Method of manufacturing NPN device A method of forming a semiconductor device is disclosed. The method includes providing a floor for a semiconductor device by utilizing a CMOS process. The method further includes providing a BiCMOS-like process on top of the floor to further fabricate the semiconduc... | 08/11/2009 |
| 7482238 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device includes steps of injecting a hole current into an N drift region while a constant voltage is applied to a P+ anode of a lateral insulated gate bipolar transistor, such that a majority of the hole current ... | 01/27/2009 |
| 7422952 | Method of forming a BJT with ESD self protection A ballasting region is placed between the base region and the collector contact of a bipolar junction transistor to relocate a hot spot away from the collector contact of the transistor. Relocating the hot spot away from the collector contact prevents the collector ... | 09/09/2008 |
| 7384802 | ESD protection device for high voltage An electrostatic discharge (ESD) protection structure and a method for forming the same are provided. The structure includes a substrate having a buried layer, and a first and a second high-voltage well region on the buried layer. The first and second high-voltage w... | 06/10/2008 |
| 7348657 | Electrostatic discharge protection networks for triple well semiconductor devices An electrostatic discharge protection network that uses triple well semiconductor devices either singularly or in a series configuration. The semiconductor devices are preferably in diode junction type configuration. ... | 03/25/2008 |
| 7271070 | Method for producing transistors The invention relates to a method for producing integrable semiconductor components, especially transistors or logic gates, using a p-doped semiconductor substrate. First of all, a mask is applied to the semiconductor substrate in order to define a window that is de... | 09/18/2007 |
| 7267430 | Heater chip for inkjet printhead with electrostatic discharge protection An inkjet printhead heater chip includes a resistor layer, a dielectric layer on the resistor layer and a cavitation layer on the dielectric layer. A grounded-gate MOSFET electrically attaches to the cavitation layer to protect the dielectric layer from breakdown du... | 09/11/2007 |
| 7217609 | Semiconductor fabrication process, lateral PNP transistor, and integrated circuit A method in the fabrication of an integrated bipolar circuit comprises the steps of: providing a p-type substrate; forming in the substrate a buried n+-type region and an n-type region above the buried n+-type region; forming field isolation areas around ... | 05/15/2007 |
| 7208386 | Drain extended MOS transistor with improved breakdown robustness A drain-extended metal-oxide-semiconductor transistor (40) with improved robustness in breakdown characteristics is disclosed. Field oxide isolation structures (29c) are disposed between the source region (30) and drain contact regions ( | 04/24/2007 |
| 7192853 | Method of improving the breakdown voltage of a diffused semiconductor junction A method is provided for forming a graded junction in a semiconductor material having a first conductivity type. Dopant having a second conductivity type opposite the first conductivity type is introduced into a selected region of the semiconductor material to defin... | 03/20/2007 |
| 7190046 | Bipolar transistor having reduced collector-base capacitance Structure and method are provided for forming a bipolar transistor. As disclosed, an intrinsic base layer is provided overlying a collector layer. A low-capacitance region is disposed laterally adjacent the collector layer. The low-capacitance region includes at lea... | 03/13/2007 |
| 7187056 | Radiation hardened bipolar junction transistor A method of forming bipolar junction devices, including forming a mask to expose the total surface of the emitter region and adjoining portions of the surface of the base region. A first dielectric layer is formed over the exposed surfaces. A field plate layer is fo... | 03/06/2007 |
| 7169660 | Lithography-independent fabrication of small openings for forming vertical mos transistor A method for formation of openings in semiconducting devices not limited by constraints of photolithography include forming a first dielectric layer over a semiconducting substrate, depositing a polysilicon layer over the first dielectric layer, forming a second die... | 01/30/2007 |
| 7141478 | Multi-stage EPI process for forming semiconductor devices, and resulting device The present invention is generally directed to a multi-stage epi process for forming semiconductor devices, and the resulting device. In one illustrative embodiment, the method comprises forming a first layer of epitaxial silicon above a surface of a semiconducting ... | 11/28/2006 |
| 7138701 | Electrostatic discharge protection networks for triple well semiconductor devices An electrostatic discharge protection network that uses triple well semiconductor devices either singularly or in a series configuration. The semiconductor devices are preferably in diode junction type configuration. ... | 11/21/2006 |
| 7098113 | Method and system for providing a power lateral PNP transistor using a buried power buss A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer; an emitter region between the first and second collector regions. Therefore slots are placed in each of the regions. Accor... | 08/29/2006 |
| 7049240 | Formation method of SiGe HBT A method for forming a SiGe HBT, which combines a SEG and Non-SEG growth, is disclosed. The SiGe base layer is deposited by a Non-SEG method. Then, the first-emitter layer is developed directly upon the SiGe base layer that has a good interface quality between the b... | 05/23/2006 |
| 7026221 | Method of forming semiconductor device with bipolar transistor having lateral structure A method of forming a semiconductor device, including forming first and second semiconductor layers of first conductivity type each disposed in a transistor forming region spaced apart from each other by a predetermined distance, so that the first semiconductor laye... | 04/11/2006 |
| 7022578 | Heterojunction bipolar transistor using reverse emitter window A heterojunction bipolar transistor (HBT), and manufacturing method therefor, comprising a semiconductor substrate having a collector region, an intrinsic base region of a compound semiconductive material over the collector region, an extrinsic base region, an emitt... | 04/04/2006 |
| 6987039 | Forming lateral bipolar junction transistor in CMOS flow A method of forming a lateral bipolar transistor without added mask in CMOS flow including a p-substrate; patterning and n-well implants; pattern and implant pocket implants for core nMOS and MOS; pattern and implants pocket implants I/O nMOS and pMOS; sidewall depo... | 01/17/2006 |
| 6949438 | Method of fabricating a bipolar junction transistor A substrate with a plurality of isolation structures for defining at least an active area thereon is provided. Ions of a first conductive type are implanted into the substrate to form a doping region in the active area. Following that, a protective layer is formed o... | 09/27/2005 |
| 6936522 | Selective silicon-on-insulator isolation structure and method A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into ... | 08/30/2005 |
| 6930009 | Laser synthesized wide-bandgap semiconductor electronic devices and circuits A laser apparatus and methods are disclosed for synthesizing areas of wide-bandgap semiconductor substrates or thin films, including wide-bandgap semiconductors such as silicon carbide, aluminum nitride, gallium nitride and diamond to produce electronic devices and ... | 08/16/2005 |
| 6927102 | Semiconductor device and method of forming a semiconductor device A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one embodiment, the top surface of the membrane has electrical terminals co... | 08/09/2005 |
| 6902967 | Integrated circuit with a MOS structure having reduced parasitic bipolar transistor action An integrated circuit having a MOS structure with reduced parasitic bipolar transistor action. In one embodiment, a MOS integrated circuit device comprises a substrate having a working surface, at least one body region and for each body region a source and a layer o... | 06/07/2005 |
| 6821870 | Heterojunction bipolar transistor and method for fabricating the same A heterojunction bipolar transistor is fabricated by stacking a Si collector layer, a SiGeC base layer and a Si emitter layer in this order. By making the amount of a lattice strain in the SiGeC base layer on the Si collector layer 1.0% or less, the band gap can be ... | 11/23/2004 |
| 6791155 | Stress-relieved shallow trench isolation (STI) structure and method for forming the same A shallow trench isolation (STI) structure in a semiconductor substrate and a method for forming the same are provided. A trench is formed in a semiconductor substrate. A first dielectric layer is formed on sidewalls of the trench. The first dielectric layer is form... | 09/14/2004 |
| 6777302 | Nitride pedestal for raised extrinsic base HBT process A method of fabricating a high-performance, raised extrinsic base HBT having a narrow emitter width is provided. In accordance with the method, a patterned nitride pedestal region and inner spacers are employed to reduce the width of an emitter opening. The reduced ... | 08/17/2004 |
| 6767842 | Implementation of Si-Ge HBT with CMOS process A semiconductor device wherein Si—Ge is the base of a bipolar transistor and a Silicon layer is the emitter. A method of making such a semiconductor device including steps of forming a Silicon dioxide layer on a Silicon substrate, using a photo resist application ... | 07/27/2004 |
| 6767810 | Method to increase substrate potential in MOS transistors used in ESD protection circuits An integrated circuit located between isolation trenches at the surface of a semiconductor chip comprising a first well of a first conductivity type having a first resistivity. This first well has a shallow buried region of higher resistivity than the first resistiv... | 07/27/2004 |
| 6706567 | High voltage device having polysilicon region in trench and fabricating method thereof A high voltage device prevents or minimizes the lowering of a maximum operating voltage range. Bulk resistances of the drift regions are reduced by forming trenches within the drift regions and filling the trenches with conductive polysilicon layers. The polysilicon... | 03/16/2004 |
| 6692982 | Optical semiconductor integrated circuit device and manufacturing method for the same In an optical semiconductor integrated circuit device in which a vertical pnp transistor and a photodiode are formed, the preferred embodiments of the present invention eliminates difficulty in performance improvement of the two elements. In an illustrati... | 02/17/2004 |
| 6638807 | Technique for gated lateral bipolar transistors An improved structure and method for gated lateral bipolar transistors are provided. Embodiments of the present invention capitalize on opposing sidewalls and adjacent conductive sidewall members to conserve available surface space on the semiconductor ch... | 10/28/2003 |
| 6569730 | High voltage transistor using P+ buried layer A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This... | 05/27/2003 |
| 6563193 | Semiconductor device A semiconductor device comprises a substrate the surface of which is formed of an insulation region, a high resistance active layer of a first conductivity type formed on the substrate, a first semiconductor region of the first conductivity type having an... | 05/13/2003 |
| 6551869 | Lateral PNP and method of manufacture A lateral PNP is disclosed in which a substrate of a first conductivity type is used. On top of the substrate a buried region of a second conductivity type is formed. A lightly doped collector region is located above the buried region. The lateral PNP als... | 04/22/2003 |
| 6524922 | Semiconductor device having increased breakdown voltage and method of fabricating same A method of fabricating bipolar junction transistors particularly suitable for electrostatic discharge protection and high voltage MOSFETs. In accordance with the invention, a mask covers bird's beaks formed between field oxide layers and doped regions of... | 02/25/2003 |
