Class 438/334 - Forming inverted transistor structure

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process forming a bipolar transistor structure in which
No. of patents: 38
Last issue date: 05/10/2011

Number	Title	Issue Date
7939417	Bipolar transistor and back-gated transistor structure and method A structure is disclosed including a substrate including an insulator layer on a bulk layer, and a bipolar transistor in a first region of the substrate, the bipolar transistor including at least a portion of an emitter region in the insulator layer. Another disclos...	05/10/2011
7320922	Integrated circuit and method for manufacturing an integrated circuit on a semiconductor chip An integrated circuit on a semiconductor chip is provided with a first bipolar transistor and a second bipolar transistor. The first bipolar transistor has a first collector region of a first conductivity type, grown by at least one epitaxial layer, and the second b...	01/22/2008
7311406	Image sensing system for a vehicle An image sensing system for a vehicle includes an imaging sensor comprising a two-dimensional array of light sensing photosensor elements, preferably formed on a semiconductor substrate, and a logic and control circuit, preferably with at least a portion of the logi...	12/25/2007
7064360	Bipolar transistor and method for fabricating it A method is provided to fabricate a bipolar transistor with a low base connection resistance, low defect density and improved scalability. Scalability is to be understood in this case as both the lateral scaling of the emitter window and the vertical scaling of the ...	06/20/2006
6815272	Bottom gate-type thin-film transistor and method for manufacturing the same In a bottom gate-type thin-film transistor manufacturing method, after ion doping, an ion stopper is removed. The ion stopper does not remain in the interlayer insulating film lying immediately above the gate electrode. The thin-film transistor has such a structure ...	11/09/2004
6569730	High voltage transistor using P+ buried layer A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This...	05/27/2003
6414371	Process and structure for 50+ gigahertz transistor High frequency performance of transistor designs is enhanced and manufacturing yield improved by removing and reducing sources of parasitic capacitance through combinations of processes from different technologies. After formation of collector, base and e...	07/02/2002
6326664	Transistor with ultra shallow tip and method of fabrication A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip comprising an ultra shallow region which extends beneath the gate electrode ...	12/04/2001
6326292	Semiconductor component and manufacturing method for semiconductor component A semiconductor includes a buried conducting layer, such as a buried collector, comprises a trench, the walls of which are covered with a layer of a material in which dopant ions diffuse faster than in monocrystalline silicon. A contact area is doped in c...	12/04/2001
5981323	Method and apparatus for protecting a device against voltage surges A structure for the protection of a high-voltage pad includes a lateral bipolar transistor, an N-type diffusion of which, connected to the pad to be protected, is made in an N-type tub with a zone that extends laterally outside the tub in the base. A P-ty...	11/09/1999
5938839	Method for forming a semiconductor device A method for forming a semiconductor device is disclosed. The method comprises the step of irradiating a laser light to a surface of a semiconductor through a mask provided on said surface in an atmosphere comprising an impurity of one conductivity type t...	08/17/1999
5914189	Protected thermal barrier coating composite with multiple coatings A composite that protects thermal barrier coatings from the deleterious effects of environmental contaminants at operational temperatures is discovered. The thermal barrier coated parts have least two outer protective coatings that decrease infiltration o...	06/22/1999
5607867	Method of forming a controlled low collector breakdown voltage transistor for ESD protection circuits An npn transistor having a low collector-base breakdown voltage. An emitter region (104, 106) of a first conductivity type is located in a semiconductor substrate (102). A base region (14) of a second conductivity type is located within the emitter region...	03/04/1997
5501992	Method of manufacturing bipolar transistor having ring-shaped emitter and base A ring-shaped emitter region is formed either in a region a little toward an inner periphery or in a region a little toward an outer periphery in an upper layer portion of a ring-shaped base region of a bipolar transistor. A conductive layer is laminated ...	03/26/1996
5478760	Process for fabricating a vertical bipolar junction transistor A process for fabricating a bipolar junction transistor by forming a trench in a silicon substrate. A lightly-doped base region is formed adjacent to the sidewalls of the trench, and a heavily-doped base region is formed under the bottom of the trench. Si...	12/26/1995
5434091	Method for making collector up bipolar transistors having reducing junction capacitance and increasing current gain This is a method of fabricating a bipolar transistor on a wafer. The method can comprise: forming a doped emitter contact layer 31 on a substrate 30; forming a doped emitter layer 32 on top of the emitter contact layer, the emitter layer doped same conduc...	07/18/1995
5399510	Method of fabricating a semiconductor device In order to simplify the structure of a power amplifying transistor and improve its high-frequency characteristics, a base electrode (7b) and a collector electrode (7c) are formed on the surface of such a power amplifying transistor, while an emitter elec...	03/21/1995
5109263	Semiconductor device with optimal distance between emitter and trench isolation A vertical bipolar transistor arrangement in which the distance between the emitter and the isolation region is kept within a range determined by the sum of emitter depth and base width (i.e., the thickness of the base in the depth direction). This keeps ...	04/28/1992
5053346	Method for making a high speed gallium arsenide transistor Vertical buried emitter heterojunction bipolar transistors having greatly reduced emitter to base junction area and collector dimensions are fabricated in a gallium arsenide substrate to form an integrated circuit structure. The ability to scale these cri...	10/01/1991
5047823	Circuit structure having a lateral bipolar transistor and its method of manufacture A circuit structure contains at least one bipolar transistor whose emitter is fashioned as a part of a doped silicon layer grown on a substrate. The doped silicon layer comprises a sidewall extending parallel to its surface normal, the sidewall being cove...	09/10/1991
4876212	Process for fabricating complimentary semiconductor devices having pedestal structures A process for fabricating complimentary semiconductor devices having pedestal structures wherein both PNP and NPN transistors are formed simultaneously on the same substrate. After polysilicon layers have been patterned and etched, various polysilicon reg...	10/24/1989
4651410	Method of fabricating regions of a bipolar microwave integratable transistor A method of fabricating bipolar integratable transistors includes a recrystallization step. A monocrystalline epitaxial layer is deposited upon a highly doped substrate and impurities are introduced into a portion of the epitaxial layer to form a first tr...	03/24/1987
4619036	Self-aligned low-temperature emitter drive-in After the extrinsic base region of a bipolar transistor has been formed, and the emitter contact has been patterned and cut, the emitter dopant is deposited or spun on, and the emitter dopant is then driven in using a short pulse of radiant energy. The ne...	10/28/1986
4617071	Method of fabricating electrically connected regions of opposite conductivity type in a semiconductor structure The two transistors of a bipolar flip-flop structure are interconnected by using a polycrystalline silicon/metal silicide sandwich structure. The polycrystalline silicon is doped to correspond to the underlying regions of the transistor structures, and un...	10/14/1986
4571275	Method for minimizing autodoping during epitaxial deposition utilizing a graded pattern subcollector The method suggests the replacement of all or part of the solid or blanket buried region, typically a subcollector region of a bipolar transistor, by a mesh or stripe shaped subcollector. During subsequent thermal processing involving growth of the epitax...	02/18/1986
4550491	Method of making substrate injection logic operator structure An SFL operator and process for its manufacture. The operator is manufactured from a low-doped P-type substrate on which are successively implanted a highly-doped P-type layer and a highly-doped N-type layer. Below a metallic collector contact of the NPN ...	11/05/1985
4502201	Semiconductor integrated circuit device and fabrication method thereof The invention discloses a semiconductor integrated circuit device characterized in that an inverse transistor element portion and a normal transistor element portion are formed in a common semiconductor layer and are separated from each other by an oxide ...	03/05/1985
4488350	Method of making an integrated circuit bipolar memory cell A static bipolar random access memory cell includes first and second transistors formed in epitaxial silicon pockets 41 and 42 in a substrate. The collectors 19 and 19' and bases 15 and 15' of the transistors are interconnected with polycrystalline silico...	12/18/1984
4260430	Method of manufacturing a semiconductor device An I2 L device is disclosed wherein the P type injector region of a PNP transistor is formed so as to be buried in an N- type epitaxial layer below the P type collector region of the PNP transistor, whereby the carrier injection effi...	04/07/1981
4199378	Method of manufacturing a semiconductor device and semiconductor device manufactured while using such a method A method of manufacturing LOCOS transistors in which base doping, emitter doping and emitter metallization are provided via the same aperture. Problems at the edge of the sunken oxide are eliminated by a two-stage doping technique so that the channel stop...	04/22/1980
4183036	Schottky-transistor-logic A Schottky-transistor-logic arrangement is disclosed which comprises a highly doped semiconductor substrate of one conductivity type. An epitaxial layer of the same conductivity type is formed on the substrate. A deep-implanted doped zone of the other con...	01/08/1980
4160988	Integrated injection logic (I-squared L) with double-diffused type injector A semiconductor structure, and method for fabrication, including a semiconductor body of one conductivity type having a major surface. A layer of opposite conductivity material is formed on said surface, said layer having an upper planar surface generally...	07/10/1979
4140559	Method of fabricating an improved substrate fed logic utilizing graded epitaxial deposition An integrated circuit having a substrate of a first conductivity type, a first layer of opposite conductivity type thereon and a second layer of said first conductivity type inversely graded on said first layer and including a heavily doped region adjacen...	02/20/1979
4118251	Process for the production of a locally high, inverse, current amplification in a planar transistor A process for the production of a locally high inverse current amplification in a preferably double diffused or implanted inversely operated transistor which includes forming a low doped epitaxial layer of one conductivity type on a high doped semiconduct...	10/03/1978
4111720	Method for forming a non-epitaxial bipolar integrated circuit A method for forming a non-epitaxial bipolar integrated circuit comprising first forming in a silicon substrate of one-type of conductivity, recessed silicon dioxide regions extending into the substrate and laterally enclosing at least one silicon substra...	09/05/1978
4082571	Process for suppressing parasitic components utilizing ion implantation prior to epitaxial deposition A process for suppressing parasitic components, in particular parasitic diodes and transistors, in integrated circuits which have, in particular, inversely operated transistors, in which a semiconductor substrate of the first conductivity type as introduc...	04/04/1978
4075039	Integrated logic circuit and method of fabrication An integrated injection logic circuit having improved operating characteristics is provided, comprising an inverted, multiple-collector transistor having base regions characterized by a central active portion surrounded by a heavily-doped extrinsic base r...	02/21/1978
4045251	Process for producing an inversely operated transistor A process for producing an inversely operated transistor in a body of semiconductor material which has arranged on its surface collector, base and emitter zones and wherein the base is doped by ion implantation so that minority charge carriers injected fr...	08/30/1977

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Class 438/334 - Forming inverted transistor structure