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| Number | Title | Issue Date |
| 8003474 | Electrically programmable fuse and fabrication method An electrically programmable fuse includes an anode, a cathode, and a fuse link conductively connecting the cathode with the anode, which is programmable by applying a programming current. The anode and the fuse link each include a polysilicon layer and a silicide l... | 08/23/2011 |
| 7442626 | Rectangular contact used as a low voltage fuse element A repair fuse element and method of construction are disclosed that eliminate or substantially reduce the disadvantages and problems associated with prior fuse elements. In one embodiment, the fuse element is constructed with a rectangular-shaped contact. The contac... | 10/28/2008 |
| 7413936 | Method of forming copper layers A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends include a portion of the first and second conductive layers, the centr... | 08/19/2008 |
| 7384824 | Structure and programming of laser fuse A method and structure for fabricating a laser fuse and a method for programming the laser fuse. The laser fuse includes a dielectric layer having two vias filled with a first self-passivated electrically conducting material. A fuse link is on top of the dielectric ... | 06/10/2008 |
| 7381594 | CMOS compatible shallow-trench efuse structure and method A semiconductor structure including at least one e-fuse embedded within a trench that is located in a semiconductor substrate (bulk or semiconductor-on-insulator) is provided. In accordance with the present invention, the e-fuse is in electrical contact with a dopan... | 06/03/2008 |
| 7354805 | Method of making electrically programmable fuse for silicon-on-insulator (SOI) technology A fuse structure and method of forming the same is described, wherein the body of the fuse is formed from a crystalline semiconductor body on an insulator, preferably of a silicon-on-insulator wafer, surrounded by a fill-in dielectric. The fill-in dielectric is pref... | 04/08/2008 |
| 7352050 | Fuse region of a semiconductor region In a fuse region of a semiconductor device, and a method of fabricating the same, the fuse region includes an interlayer insulating layer on a semiconductor substrate, a plurality of fuses on the interlayer insulating layer disposed in parallel with each other, a bl... | 04/01/2008 |
| 7335537 | Method of manufacturing semiconductor device including bonding pad and fuse elements A method of manufacturing a semiconductor device includes forming a first insulating film supported by a semiconductor substrate, forming an aluminum layer supported by the first insulating film, etching the aluminum layer to form a bonding pad and fuse elements, de... | 02/26/2008 |
| 7268068 | Semiconductor device and manufacturing method thereof A semiconductor device comprises a multiple insulation layer structure in which multiple insulation layers each having interconnection layer are built up and either one of the interconnection layer forming a fuse is blown in order to select a spare cell to relieve a... | 09/11/2007 |
| 7242072 | Electrically programmable fuse for silicon-on-insulator (SOI) technology A fuse structure and method of forming the same is described, wherein the body of the fuse is formed from a crystalline semiconductor body on an insulator, preferably of a silicon-on-insulator wafer, surrounded by a fill-in dielectric. The fill-in dielectric is pref... | 07/10/2007 |
| 7118951 | Method of isolating the current sense on power devices while maintaining a continuous stripe cell An integrated circuit die includes an active area having source dopants and contacts. An active area metal layer overlies the active area. A sense area is disposed on the die. A sense area metal layer overlies the sense area. A plurality of polysilicon gate stripes,... | 10/10/2006 |
| 7109105 | Methods of making semiconductor fuses Fuses for integrated circuits and semiconductor devices and methods for using the same. The semiconductor fuse contains two conductive layers, an overlying and underlying refractory metal nitride layer, on an insulating substrate. The semiconductor fuse may be fabri... | 09/19/2006 |
| 7087974 | Semiconductor integrated circuit including anti-fuse and method for manufacturing the same An anti-fuse is manufactured by forming an isolation region including an insulating material layer buried in a surface of a device formation region on a surface of a semiconductor substrate, and by forming diffusion regions at both sides of the isolation region, the... | 08/08/2006 |
| 7067897 | Semiconductor device A semiconductor device comprising a substrate, a plurality of dielectric films formed on the substrate, laid one upon another, and a fuse interconnect-wire formed above the substrate and covered with a predetermined one of the dielectric films, and including a fuse ... | 06/27/2006 |
| 7067359 | Method of fabricating an electrical fuse for silicon-on-insulator devices A method and apparatus for providing an electrical fuse is provided. An electrical fuse is patterned from the active layer of a semiconductor-on-insulator (SOI) wafer. One shape of the electrical fuse may be a first and second portion electrically coupled via a thir... | 06/27/2006 |
| 7005727 | Low cost programmable CPU package/substrate A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends include a portion of the first and second conductive layers, the centr... | 02/28/2006 |
| 6991971 | Method for fabricating a triple damascene fuse A method for fabricating a fuse for a semiconductor device. The method including: providing a substrate; forming a first dielectric layer on a top surface of said substrate; forming a dielectric mandrel on a top surface of said first dielectric layer; forming a seco... | 01/31/2006 |
| 6933591 | Electrically-programmable integrated circuit fuses and sensing circuits Programmable fuses for integrated circuits are provided. The fuses may be based on polysilicon or crystalline silicon fuse links coated with silicide or other conductive thin films. Fuses may be formed on silicon-on-insulator (SOI) substrates. A fuse may be blown by... | 08/23/2005 |
| 6913954 | Programmable fuse device A fuse device including a transistor having a source, drain, and gate. The gate includes a first and second gate contact. A current may be run from the first gate contact to the second gate contact to heat the gate. The current through the gate indirectly heats the ... | 07/05/2005 |
| 6900516 | Semiconductor fuse device An increased number of fuses per area are provided in this semiconductor device while complying with the predetermined distance between the fuses. The device having a first patterned, conductive interconnect plane on a passivated substrate; a second patterned, condu... | 05/31/2005 |
| 6878614 | Methods of forming integrated circuit devices including fuse wires having reduced cross-sectional areas and related structures A method of forming an integrated circuit device can include forming a plurality of fuse wires on an integrated circuit substrate, and forming an insulating layer on the integrated circuit substrate and on the plurality of fuse wires so that the fuse wires are betwe... | 04/12/2005 |
| 6787878 | Semiconductor device having a potential fuse, and method of manufacturing the same In a semiconductor device, an active region is formed in a semiconductor substrate separated by a plurality of isolation regions. A plurality of surface insulating films of different thickness are formed separately on the active region. A plurality of conductive fil... | 09/07/2004 |
| 6774456 | Configuration of fuses in semiconductor structures with Cu metallization A configuration of fuses in a semiconductor structure having Cu metallization planes is provided. The semiconductor structure has an Al metal layer on the topmost interconnect plane for providing Al bonding pads. The fuses are configured as Al fuses and, in the semi... | 08/10/2004 |
| 6746947 | Post-fuse blow corrosion prevention structure for copper fuses A structure and method of fabricating a semiconductor corrosion resistant metal fuse line including a refractory liner which can also act as a resistor is disclosed. Fabrication is accomplished using damascene process. The metal structure can be formed on a semicond... | 06/08/2004 |
| 6667533 | Triple damascene fuse Disclosed is a conductive fuse for a semiconductor device, comprising: a pair of contact portions integrally connected to a fusible portion by connecting portions; the contact portions thicker than the connecting portions and the connecting portions thick... | 12/23/2003 |
| 6656826 | Semiconductor device with fuse to be blown with energy beam and method of manufacturing the semiconductor device A semiconductor device has a fuse to be blown with an energy beam. The semiconductor device has copper wiring levels formed on a semiconductor substrate on which semiconductor elements are formed, an uppermost wiring level formed on said copper wiring lev... | 12/02/2003 |
| 6624499 | System for programming fuse structure by electromigration of silicide enhanced by creating temperature gradient The present invention provides a system, apparatus and method of programming via electromigration. A semiconductor fuse which includes a cathode and an anode coupled by a fuse link having an electrically conductive component, such as silicide, is coupled ... | 09/23/2003 |
| 6559042 | Process for forming fusible links A process for forming fusible links in an integrated circuit includes forming the fusible link in the last metallization layer. The process can be employed in the fabrication of integrated circuits employing copper metallization and low k dielectric mater... | 05/06/2003 |
| 6548358 | Electrically blowable fuse with reduced cross-sectional area A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space betwe... | 04/15/2003 |
| 6534780 | Array of ultra-small pores for memory cells A method for fabricating an array of ultra-small pores for use in chalcogenide memory cells. A layer of a first material is applied onto a substrate. A portion of the layer of the first material is then removed to define an upper surface with vertical sur... | 03/18/2003 |
| 6528378 | Semiconductor device To provide a super high-speed heterojunction bipolar transistor, a semiconductor device including such a heterojunction bipolar transistor has a structure wherein a subcollector layer, collector layer, base layer, emitter layer (InGaP layer) and emitter c... | 03/04/2003 |
| 6518140 | Manufacturing methods for defect removable semiconductor devices A defect removable semiconductor element and the manufacturing method thereof are provided with a protective layer covering fuses exposed at a part of the redundancy memory cell region, the layer being thinner than the one covering the main memory cell re... | 02/11/2003 |
| 6518643 | Tri-layer dielectric fuse cap for laser deletion A substrate having at least one fuse in a fuse layer. An upper etch-stop layer over the fuse, a lower etch-stop layer having a different etch-chemistry over the fuse and, optionally, a diffusion barrier layer immediately over the fuse. The lower etch-stop... | 02/11/2003 |
| 6469363 | Integrated circuit fuse, with focusing of current An integrated circuit fuse is formed on a substrate by etching a polysilicon, metal or alloy layer deposited thereon to include a central region, at the end of which are zones with electrical contacts. The central region has at least two first electricall... | 10/22/2002 |
| 6432760 | Method and structure to reduce the damage associated with programming electrical fuses An improved fuse structure in an integrated circuit (IC) structure is made by forming a gate stack comprised of layers of polysilicon and a silicide. Subsequent to the formation of the silicide layer, an etch stop silicon nitride layer is deposited over t... | 08/13/2002 |
| 6433404 | Electrical fuses for semiconductor devices A fuse for semiconductor devices, in accordance with the present invention, includes a cathode formed from a first material, an anode formed from a second material and a fuse link connecting the cathode and the anode and formed from the second material. T... | 08/13/2002 |
| 6420216 | Fuse processing using dielectric planarization pillars An electrical fuse structure comprises a semiconductor substrate; at least one electrically insulating layer over the semiconductor substrate having a portion thereof containing electrical wiring and another, adjacent portion thereof substantially free of... | 07/16/2002 |
| 6410367 | Fuse for use in a semiconductor device, and semiconductor devices including the fuse A metal silicide fuse for a semiconductor device. The fuse includes a conductive region positioned adjacent a common well of a first conductivity type, a terminal region positioned adjacent a well of a second conductivity type, and a narrowed region locat... | 06/25/2002 |
| 6362514 | Semiconductor device There is described a semiconductor device having a copper fuse which prevents damage to a silicon substrate beneath the copper fuse, which would otherwise be caused by a laser beam radiated to blow the copper fuse. A light absorbing layer is formed on the... | 03/26/2002 |
| 6355967 | Semiconductor device and method of manufacturing the same In the fuse element structure of the semiconductor device, the first insulating film region is provided in a groove-like manner in the semiconductor substrate. Further, the fuse element is formed on the first insulating film region, and the second insulat... | 03/12/2002 |
