Class 438/331 - Having same doping as emitter or collector

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process wherein the resistor region has the same doping
No. of patents: 37
Last issue date: 01/01/2008

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Number	Title	Issue Date
7314786	Metal resistor, resistor material and method A metal resistor and resistor material and method of forming the metal resistor are disclosed. The metal resistor may include an infused metal selected from the group consisting of: copper (Cu) infused with at least one of silicon (Si), nitrogen (N2), car...	01/01/2008
7208814	Resistive device and method for its production A resistive device includes a resistive region of a semiconductor material that includes a first region and a second region, wherein the first region has a higher dopant concentration than the second region, and wherein a resistance-determining width of a current pa...	04/24/2007
7148556	High performance diode-implanted voltage-controlled poly resistors for mixed-signal and RF applications A p-type polysilicon resistor formed in the inter-level dielectric layer contains an implanted diode. A positive voltage applied to the diode modulates the depletion region of the diode and changes the absolute resistance of the p-type polysilicon resistor. This mod...	12/12/2006
7129099	Method for manufacturing semiconductor device A manufacturing method for a semiconductor device which is capable of manufacturing the semiconductor device with a high quality in high yields while reducing variations in electric characteristic is disclosed. The manufacturing method according to the present inven...	10/31/2006
7098113	Method and system for providing a power lateral PNP transistor using a buried power buss A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer; an emitter region between the first and second collector regions. Therefore slots are placed in each of the regions. Accor...	08/29/2006
7041566	Method for forming inductor in semiconductor device The present invention relates to a method for forming an inductor in a semiconductor device. The method comprises the steps of forming a first metal layer on a semiconductor substrate in which a predetermined structure is formed, and then patterning the first metal ...	05/09/2006
6979879	Trim zener using double poly process In a zener zap diode device and a system for making such a device using a double poly process, p+ and n+regions are formed in a tub by means of p-doped and n-doped polysilicon regions, and a p-n junction is formed between the p+ region and an n-tub or between the n+...	12/27/2005
6890826	Method of making bipolar transistor with integrated base contact and field plate A method of manufacturing a bipolar junction transistor results in an integrated polysilicon base contact and field plate element minimally spaced from a polysilicon emitter contact by using a single mask to define respective openings for these elements. In particul...	05/10/2005
6867106	Semiconductor device and method for fabricating the same The semiconductor device comprises: a conducting layer including: a channel region; a source region and a drain region sandwiching the channel region; and a body region connected to the channel region and being adjacent to the source region and the drain region; a g...	03/15/2005
6639300	Semiconductor integrated circuit having an integrated resistance region A semiconductor integrated circuit device comprises an active device and a resistance element formed monolithically on a common substrate wherein the resistance element includes a dummy pattern having a layered structure identical with a layered structure...	10/28/2003
6602755	Method for manufacturing a compact bipolar transistor structure A bipolar transistor structure that includes a semiconductor material substrate that has a bottom substrate and base region of a first conductivity type and a buried layer, collector region and sink region of a second conductivity type. The substrate has ...	08/05/2003
6524894	Semiconductor device for use in power-switching device and method of manufacturing the same An N+ buffer layer formed on the underside of an N- layer includes an inactive region having incompletely activated ions and an active region having highly activated ions. The carrier concentration of the active region is higher than...	02/25/2003
6511889	Reference voltage supply circuit having reduced dispersion of an output voltage A reference voltage supply circuit is provided with a PNP transistor. The PNP transistor has an N-type well for a base formed at a surface of a P-type semiconductor substrate. The reference voltage supply circuit is further provided with a resistor elemen...	01/28/2003
6421224	Micro-structure capacitor The invention discloses a micro-structure capacitor formed by joining the metal layer of a multi-porous micro-structure. A substrate is used as an etching stop layer when producing the capacitor. Therefore, pores with low aspect ratio and uniform size are...	07/16/2002
6384433	Voltage variable resistor from HBT epitaxial layers A voltage variable resistor formed on heterojunction bipolar transistor epitaxial material includes a current channel made on emitter material. Emitter mesas separated by a recess provide the contacts for the voltage variable resistor. Each mesa is topped...	05/07/2002
6077752	Method in the manufacturing of a semiconductor device A method of manufacturing a bipolar transistor having a self-registered base-emitter structure is provided. The method involves the steps of: depositing a layer of amorphous silicon on a substrate of crystalline silicon having an upper region of a first c...	06/20/2000
5854116	Semiconductor apparatus The present invention relates to a semiconductor apparatus adapted to a ultrahigh density integration process. A semiconductor apparatus of the present invention is characterized by including a high concentration impurity layer with the same type of condu...	12/29/1998
5624854	Method of formation of bipolar transistor having reduced parasitic capacitance Vertically stacked regions of n-type and p-type conductivity are formed around bipolar and field effect transistors to reduce parasitic capacitance between the semiconductor device and surrounding well regions. Under reverse bias a portion of the vertical...	04/29/1997
5298440	Method of fabrication of transistor device with increased breakdown voltage A bipolar lateral device is disclosed having a high BVceo. The device is formed according to a single polysilicon process. In one embodiment silicide is excluded from the surface of the N+ doped polysilicon protecting the N- base width region o...	03/29/1994
5139961	Reducing base resistance of a BJT by forming a self aligned silicide in the single crystal region of the extrinsic base A high performance bipolar transistor and a method of fabrication. Base resistance is reduced by a self-aligned silicide formed in the single-crystal region of the extrinsic base, thereby eliminating the polysilicon to single-crystal contact resistance as...	08/18/1992
5098854	Process for forming self-aligned silicide base contact for bipolar transistor A self-aligned silicide base contact structure for a bipolar transistor, and a process for fabricating the structure are disclosed. The structure has four key elements: a base region 36, a polycrystalline silicon emitter contact region 50, a spacer oxide ...	03/24/1992
5057443	Method for fabricating a trench bipolar transistor A bipolar transistor formed in a trench depression such that a single impurity diffusing step is effective to form a buried collector layer electrically connected to a vertical collector conductor. The lateral diffusion forming the vertical collector cond...	10/15/1991
5045483	Self-aligned silicided base bipolar transistor and resistor and method of fabrication A bipolar transistor and resistor are provided. Fabrication includes using a high temperature oxide to form sidewall spacers for the transistor contacts and/or to overlay the resistor portion of the device. Deposition of the HTO is combined with dopant dr...	09/03/1991
4935375	Method of making a semiconductor device A structured semiconductor body based on a Si substrate and having monocrystalline semiconductor regions and barrier regions which contain polycrystalline silicon which have preferably been produced in an Si-MBE process. The barrier regions are provided t...	06/19/1990
4892839	Method of manufacturing a semiconductor device with polysilicon resistors and field plate A method of manufacturing a semiconductor device in which a base of a second conductivity type is provided in a semiconductor substrate of a first conductivity type, which operates as a collector. An emitter of the first conductivity type is provided in t...	01/09/1990
4888306	Method of manufacturing a bipolar transistor A semiconductor device comprising a semiconductor substrate with at least one semiconductor region formed in it, a polycrystalline silicon layer formed in contact with the semiconductor region and a metal layer formed on the polycrystalline silicon layer....	12/19/1989
4849344	Enhanced density modified isoplanar process An improved process for fabricating modified isoplanar integrated circuits with enhanced density incorporates a number of interactive and co-acting process steps. First, oxide isolation of epitaxial islands is effected in a two step process, forming a thi...	07/18/1989
4567501	Resistor structure in integrated injection logic An I2 L semiconductor device in which a p-type buried layer is formed on an n+ type silicon substrate by diffusion of boron, an epitaxial n-type layer is grown on the p-type buried layer, a p+ type region is formed in a ...	01/28/1986
4509250	Process for manufacturing a monolithic integrated circuit comprising at least one bipolar planar transistor In the process according to the invention, in addition to the conventional two photoresist processes for opening the contact holes and for manufacturing the interconnecting pattern, two photoresist processes are used with one photoresist mask each for man...	04/09/1985
4411708	Method of making precision doped polysilicon vertical ballast resistors by multiple implantations The structure and associated fabrication processes disclosed provide a resistive element directly over a specific semiconductor region. Use of such a structure in a high current device ballasts emitter fingers to improve the maximum current flow of the de...	10/25/1983
4316319	Method for making a high sheet resistance structure for high density integrated circuits A high sheet resistance structure for high density integrated circuits and the method for manufacturing such structure is given. The structure includes a silicon region separated from other silicon regions by a dielectric barrier surrounding the region. A...	02/23/1982
4260436	Fabrication of moat resistor ram cell utilizing polycrystalline deposition and etching A RAM cell having a pair of transistors formed in two adjacent wells laterally separated from each other and surrounded laterally by a common doped polycrystalline semiconductor moat. Dielectrical insulation separate the wells from the moat. The moat is d...	04/07/1981
4228450	Buried high sheet resistance structure for high density integrated circuits with reach through contacts A high sheet resistance structure for high density integrated circuits and the method for manufacturing such structure is given. The structure includes a silicon region separated from other silicon regions by a dielectric barrier surrounding the region. A...	10/14/1980
4070748	Integrated circuit structure having semiconductor resistance regions A semiconductor integrated circuit which is reduced in size by having active and/or passive elements in an epitaxial layer having a [100] crystallographic surface, and having anisotropically etched regions with sloped [111] crystallographic surface walls ...	01/31/1978
4057894	Controllably valued resistor A monolithic semiconductor device including a resistor comprising a first region of one type conductivity, has means for controllably establishing the value of the resistor comprising two additional regions of the opposite type conductivity disposed respe...	11/15/1977
4021270	Double master mask process for integrated circuit manufacture A double master mask process for fabricating semiconductor integrated circuits is provided in which selectively etchable dielectric layers and ion implanted resistors are used to form dense integrated circuits with a minimum number of critical alignments....	05/03/1977
3959040	Compound diffused regions for emitter-coupled logic circuits There is provided a method and apparatus for use in fabrication of emitter-coupled logic circuits in integrated circuit form in which the base regions for transistor-transistor logic transistors and tub regions for emitter resistors for use in these circu...	05/25/1976

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Class 438/331 - Having same doping as emitter or collector