Bizarre Patents
Smoking Cessation Lighter and Method
A lighter for tobacco products suppresses the urge to smoke by operant conditioning.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8399331 | Laser processing for high-efficiency thin crystalline silicon solar cell fabrication Laser processing schemes are disclosed for producing various types of hetero-junction and homo-junction solar cells. The methods include base and emitter contact opening, selective doping, and metal ablation. Also, laser processing schemes are disclosed that are sui... | 03/19/2013 |
| 8343843 | Monolithic microwave integrated circuit device and method for forming the same Provided are a monolithic microwave integrated circuit device and a method for forming the same. The method include: forming an HBT on a substrate; forming a wiring of the HBT and a bottom electrode of a capacitor on the substrate, with a first metal, the bottom ele... | 01/01/2013 |
| 7638405 | High voltage sensor device In one embodiment, a high voltage element is formed overlying a doped semiconductor region that can be depleted during the operation of the high voltage element. ... | 12/29/2009 |
| 7579251 | Aerosol deposition process A circuit substrate includes a passive element and an interconnection pattern, wherein any of the passive element and the interconnection pattern is formed by an aerosol deposition process that uses aerosol of a fine particle material. ... | 08/25/2009 |
| 7531416 | Thick film capacitors on ceramic interconnect substrates Thick-film capacitors are formed on ceramic interconnect substrates having high capacitance densities and other desirable electrical and physical properties. The capacitor dielectrics are fired at high temperatures. ... | 05/12/2009 |
| 7446011 | Array of cells including a selection bipolar transistor and fabrication method thereof A cell array is formed by a plurality of cells each including a selection bipolar transistor and a storage component. The cell array is formed in a body including a common collector region of P type; a plurality of base regions of N type, overlying the common collec... | 11/04/2008 |
| 7416904 | Method for forming dielectric layer of capacitor A fabrication method for forming a semiconductor device having a capacitor is provided. A capacitor dielectric layer is formed by depositing a first layer and a second layer. The second layer is a major portion of the capacitor dielectric layer. The first layer acts... | 08/26/2008 |
| 7413994 | Hydrogen and oxygen based photoresist removal process The present invention provides a photoresist removal process and a method for manufacturing an interconnect using the same. One embodiment of the photoresist removal process includes, among other steps, providing a low dielectric constant (k) substrate having a phot... | 08/19/2008 |
| 7341919 | Capacitor element, manufacturing method therefor, semiconductor device substrate, and semiconductor device A capacitor element configured to mount a semiconductor element thereon includes a base. A capacitor part is provided on the base. The base is made of a resin whose coefficient of linear expansion is adjusted in accordance with a coefficient of linear expansion of t... | 03/11/2008 |
| 7314786 | Metal resistor, resistor material and method A metal resistor and resistor material and method of forming the metal resistor are disclosed. The metal resistor may include an infused metal selected from the group consisting of: copper (Cu) infused with at least one of silicon (Si), nitrogen (N2), car... | 01/01/2008 |
| 7314780 | Semiconductor package, method of production of same, and semiconductor device A semiconductor package, provided with a multilayer interconnect structure, for mounting a semiconductor chip on its top surface, wherein a topmost stacked structure of the multilayer interconnect structure includes a capacitor structure, the capacitor structure hav... | 01/01/2008 |
| 7306999 | High voltage sensor device and method therefor In one embodiment, a high voltage element is formed overlying a doped semiconductor region that can be depleted during the operation of the high voltage element. ... | 12/11/2007 |
| 7288826 | Semiconductor integrated circuit device The bottom side of an N type silicon substrate is connected to a power supply terminal, a second P type epitaxial layer is formed on all sides of the N type silicon substrate, and a device forming portion is provided on the second P type epitaxial layer. A first P t... | 10/30/2007 |
| 7276420 | Method of manufacturing a passive integrated matching network for power amplifiers An impedance matching network is integrated on a first die and coupled to a second die, with the first and second dies mounted on a conductive back plate. The impedance matching network comprises a first inductor bridging between the first and second dies, a second ... | 10/02/2007 |
| 7271051 | Methods of forming a plurality of capacitor devices The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conduc... | 09/18/2007 |
| 7268028 | Well isolation trenches (WIT) for CMOS devices A well isolation trenches for a CMOS device and the method for forming the same. The CMOS device includes (a) a semiconductor substrate, (b) a P well and an N well in the semiconductor substrate, (c) a well isolation region sandwiched between and in direct physical ... | 09/11/2007 |
| 7253495 | Integrated circuit package with air gap An integrated circuit (IC) package comprises an IC wafer comprising a circuit. A “C”-shaped layer is arranged adjacent to the substrate and that creates an air gap between the “C”-shaped layer and the circuit of the IC wafer. ... | 08/07/2007 |
| 7250348 | Apparatus and method for packaging semiconductor devices using a patterned photo sensitive film to reduce stress buffering A method and apparatus for packaging semiconductor devices using patterned laminate films to reduce stress buffering. The method includes fabricating a semiconductor die having thin film resistors and bond pads formed on an active surface. A film layer is formed ont... | 07/31/2007 |
| 7233516 | Semiconductor device and method for fabricating the same A semiconductor device includes a first DRAM section formed on a semiconductor substrate and composed of a plurality of first memory cells and a second DRAM section formed on the semiconductor substrate and composed of a plurality of second memory cells. The operati... | 06/19/2007 |
| 7226845 | Semiconductor constructions, and methods of forming capacitor devices The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conduc... | 06/05/2007 |
| 7202648 | Fully integrated DC-to-DC regulator utilizing on-chip inductors with high frequency magnetic materials An fully integrated DC-to-DC switching converter having an inductor, where the inductor has magnetic material that may be amorphous CoZrTa, CoFeHfO, CoAlO, FeSiO, CoFeAlO, CoNbTa, CoZr, and other amorphous cobalt alloys. The magnetic material allows for a relatively... | 04/10/2007 |
| 7183216 | Methods to form oxide-filled trenches A thermal oxidation process is used to fill trenches with an oxide; however, the oxidation process consumes some of the silicon. The embodiments herein advantageously apply this tendency for the oxidation process to consume silicon so as to convert all the silicon s... | 02/27/2007 |
| 7169661 | Process of fabricating high resistance CMOS resistor A process of forming a high resistance CMOS resistor with a relatively small die size is provided. According to an aspect of the present invention, the process of fabricating a high resistance resistor is a standard CMOS process that does not require any additional ... | 01/30/2007 |
| 7160772 | Structure and method for integrating MIM capacitor in BEOL wiring levels A method for integrating a metal-insulator-metal (MIM) capacitor in back end of line (BEOL) wiring levels of a semiconductor device includes forming an isolating layer over a lower wiring level, forming a bottom electrode of the capacitor on the isolating layer, and... | 01/09/2007 |
| 7151036 | Precision high-frequency capacitor formed on semiconductor substrate A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A s... | 12/19/2006 |
| 7141865 | Low noise semiconductor amplifier A Low Noise semiconductor amplifier structure formed from layers of differently doped semiconductor material. This structure when properly biased will amplify voltage signals applied to the input terminal (Base1 or signal-base), and provide the same signal, a... | 11/28/2006 |
| 7135375 | Varactors for CMOS and BiCMOS technologies Varactors are provided which have a high tunability and/or a high quality factor associated therewith as well as methods for fabricating the same. One type of varactor disclosed is a quasi hyper-abrupt base-collector junction varactor which includes a substrate havi... | 11/14/2006 |
| 7135415 | Insulated structure of a chip array component and fabrication method of the same An insulated structure of a chip array component and fabrication method of the same, the element is fabricated by enclosing its main body with a dense layer of high surface insulation resistance material, and then exposing the portions of the main body where termina... | 11/14/2006 |
| 7087999 | Semiconductor protection element, semiconductor device and method for manufacturing same A semiconductor protection element is provided in which no heat generation occurs in a concentrated manner, in a region having a high resistance value even when electrostatic discharge (ESD) is applied, without an increase in an area of the semiconductor device. The... | 08/08/2006 |
| 7084485 | Method of manufacturing a semiconductor component, and semiconductor component formed thereby A method of manufacturing a semiconductor component includes: providing a semiconductor substrate (210, 510); forming a trench (130, 430) in the semiconductor substrate to define a plurality of active areas separated from each other by the trench; form... | 08/01/2006 |
| 7078304 | Method for producing an electrical circuit An electrical circuit is formed by forming and patterning a conductive layer on a substrate, forming and patterning a conductive layer on another substrate, depositing a dielectric layer on at least a portion of one of conductive layers, mounting an integrated circu... | 07/18/2006 |
| 7064416 | Semiconductor device and method having multiple subcollectors formed on a common wafer A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors... | 06/20/2006 |
| 7045426 | Vertical type power MOSFET having trenched gate structure A power MOSFET comprising a drain layer of a first conductivity type, a drift layer of the first conductivity type provided on the drain layer, a base layer of a first or a second conductivity type provided on the drift layer, a source region of the first conductivi... | 05/16/2006 |
| 7041565 | Method for fabricating a capacitor in a semiconductor device A method for fabricating a capacitor in a semiconductor device that includes providing a semiconductor substrate, forming at least one shallow trench isolation structure in the semiconductor substrate, forming a tunnel oxide layer over the semiconductor substrate, d... | 05/09/2006 |
| 7038249 | Horizontal current bipolar transistor and fabrication method A bipolar transistor structure for use in integrated circuits where the active device is processed on the sidewall of an n-hill so that the surface footprint does not depend on the desired area of active device region (emitter area). This structure, which is referre... | 05/02/2006 |
| 7033900 | Protection of integrated circuit gates during metallization processes In one embodiment, a first transistor is configured to switch ON to discharge accumulated charges on an interconnect line during a metallization process. This advantageously protects a second transistor, which is coupled to the interconnect line, from charge buildup... | 04/25/2006 |
| 7025615 | Fabrication method, varactor, and integrated circuit A method in the fabrication of an integrated bipolar circuit for forming a p/n-junction varactor is disclosed. The method featuring the steps of providing a p-doped substrate (10; 10, 41); forming a buried n+-doped region (31) in the substra... | 04/11/2006 |
| 6995457 | Wiring structure and manufacturing method therefor, semiconductor device including wiring structure and wiring board A wiring structure including a transmission line structure capable of simplifying a manufacturing process is obtained. This wiring structure comprises a first trench formed on a first insulator film provided on a substrate, a first wire formed in the extensional dir... | 02/07/2006 |
| 6995053 | Vertical thin film transistor A vertical thin-film transistor (V-TFT) is provided along with a method for forming the V-TFT. The method comprises: providing a substrate made from a material such as Si, quartz, glass, or plastic; conformally depositing an insulating layer overlying the substrate;... | 02/07/2006 |
| 6991982 | Method of manufacturing a semiconductor non-volatile memory A method of manufacturing a semiconductor device comprising a non-volatile memory with memory transistors and selection transistors. In this method a semiconductor body is provided with strip-shaped active regions (4) which are mutually isolated by field-oxid... | 01/31/2006 |
