Quotables
"Inventing is a combination of brains and materials. The more brains you use, the less material you need."
Charles Kettering
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7442617 | Method for manufacturing bipolar transistor A method for manufacturing a bipolar transistor comprising: forming a device isolation layer in a device isolation region of a semiconductor substrate having therein first and second well regions having a first conductivity; implanting ions of a second conductivity ... | 10/28/2008 |
| 7422952 | Method of forming a BJT with ESD self protection A ballasting region is placed between the base region and the collector contact of a bipolar junction transistor to relocate a hot spot away from the collector contact of the transistor. Relocating the hot spot away from the collector contact prevents the collector ... | 09/09/2008 |
| 7348250 | Bipolar structure with two base-emitter junctions in the same circuit Bipolar integrated circuits employing SiGe technology incorporate the provision of mask-selectable types of bipolar transistors. A high-performance/high variability type has a thin base in which the diffusion from the emitter intersects the base dopant diffusion wit... | 03/25/2008 |
| 7329584 | Method for manufacturing bipolar transistor A method for manufacturing a bipolar transistor includes: forming a device isolation layer on a semiconductor substrate having first and second well regions of a first conductivity therein; implanting ions of a second conductivity in the first well to form a third w... | 02/12/2008 |
| 7252864 | Optical film for display devices Disclosed is an optical film that comprises certain radiation cured (meth)acrylate binders and, desirably, irregular semicrystalline asymmetric particles. ... | 08/07/2007 |
| 7243504 | Cogeneration system A cogeneration system including an engine, which drives a generator to generate electricity, a cooling/heating unit using a heat pump type refrigerant cycle, in which a refrigerant is circulated through at least one compressor, a four-way valve, a first outdoor heat... | 07/17/2007 |
| 7217609 | Semiconductor fabrication process, lateral PNP transistor, and integrated circuit A method in the fabrication of an integrated bipolar circuit comprises the steps of: providing a p-type substrate; forming in the substrate a buried n+-type region and an n-type region above the buried n+-type region; forming field isolation areas around ... | 05/15/2007 |
| 7064413 | Fin-type resistors A method of forming a Fin structure including a resistor present in the thin vertically oriented semiconductor body is provided. The method includes the steps of forming at least one vertically-oriented semiconductor body having exposed vertical surfaces on a substr... | 06/20/2006 |
| 6987039 | Forming lateral bipolar junction transistor in CMOS flow A method of forming a lateral bipolar transistor without added mask in CMOS flow including a p-substrate; patterning and n-well implants; pattern and implant pocket implants for core nMOS and MOS; pattern and implants pocket implants I/O nMOS and pMOS; sidewall depo... | 01/17/2006 |
| 6979876 | Method for forming isolation layer of semiconductor device A method for forming an isolation layer of a semiconductor device which is capable of improving isolation characteristics of a highly integrated semiconductor device. The method includes the steps of forming a first insulating layer on a substrate; forming both a fi... | 12/27/2005 |
| 6972237 | Lateral heterojunction bipolar transistor and method of manufacture using selective epitaxial growth A method for manufacturing a heterojunction bipolar transistor is provided. An intrinsic collector structure is formed on a substrate. An extrinsic base structure partially overlaps the intrinsic collector structure. An intrinsic base structure is formed adjacent th... | 12/06/2005 |
| 6864540 | High performance FET with elevated source/drain region The invention includes a field effect transistor (FET) on an insulator layer, and integrated circuit (IC) on SOI chip including the FETs and a method of forming the IC. The FETs include a thin channel with raised source/drain (RSD) regions at each end on an insulato... | 03/08/2005 |
| 6861325 | Methods for fabricating CMOS-compatible lateral bipolar junction transistors A method for fabricating a lateral bipolar junction transistor in an active area of a substrate includes forming a base structure directly on a central portion of the active area without a gate oxide layer being formed on the substrate. The method also includes impl... | 03/01/2005 |
| 6800531 | Method of fabricating a bipolar transistor A thin InGaAs contact layer is provided for the collector of a heterojunction bipolar transistor (HBT) above an InP sub-collector. The contact layer provides a low resistance contact mechanism and a high thermal conductivity path for removing device heat though the ... | 10/05/2004 |
| 6784065 | Bipolar transistor with ultra small self-aligned polysilicon emitter and method of forming the transistor A low-power bipolar transistor is formed to have an intrinsic emitter region with a sub-lithographic width, and an oxide layer that is self aligned to an overlying extrinsic emitter. The small extrinsic emitter region reduces the maximum current that can flow throug... | 08/31/2004 |
| 6610578 | Methods of manufacturing bipolar transistors for use at radio frequencies A bipolar transistor of type NPN has an active region at the surface of the component, which is surrounded, as seen along the surface of the component, in the conventional way by thick field oxide areas. The active region is partly covered by an electrica... | 08/26/2003 |
| 6573149 | Semiconductor device having a metal gate with a work function compatible with a semiconductor device The present invention provides a semiconductor device located on a semiconductor substrate having opposite types of first and second transistors formed thereon. The device preferably includes a first gate electrode that includes a first metal gate electro... | 06/03/2003 |
| 6518139 | Power semiconductor device structure with vertical PNP transistor A power semiconductor device structure formed in a chip of semiconductor material includes an N-type substrate and an N-type epitaxial layer. The structure comprises a P-type insulation region which forms a pocket in which control circuitry is formed, and... | 02/11/2003 |
| 6492238 | Bipolar transistor with raised extrinsic base fabricated in an integrated BiCMOS circuit A process for forming a bipolar transistor with a raised extrinsic base, an emitter, and a collector integrated with a CMOS circuit with a gate. An intermediate semiconductor structure is provided having CMOS and bipolar areas. An intrinsic base layer is ... | 12/10/2002 |
| 6489211 | Method of manufacturing a semiconductor component A method of manufacturing a semiconductor component includes providing a composite substrate (300) with a dielectric portion and a semiconductor portion and growing an epitaxial layer (400) over the composite substrate. The epitaxial layer has a polycryst... | 12/03/2002 |
| 6384433 | Voltage variable resistor from HBT epitaxial layers A voltage variable resistor formed on heterojunction bipolar transistor epitaxial material includes a current channel made on emitter material. Emitter mesas separated by a recess provide the contacts for the voltage variable resistor. Each mesa is topped... | 05/07/2002 |
| 6358786 | Method for manufacturing lateral bipolar mode field effect transistor A lateral bipolar field effect transistor having a drift region of a first conductivity formed on a silicon-on insulation substrate with a buried insulation layer, a gate region of a second conductivity formed over and from the buried insulation layer sep... | 03/19/2002 |
| 6352887 | Merged bipolar and CMOS circuit and method A method for fabricating a BiCMOS integrated circuit. The method includes the steps of forming in a single implantation step a base region 211 of a bipolar transistor and a p-well 212 of an n-channel MOS transistor; and forming in a single implantation st... | 03/05/2002 |
| 6337220 | Ion implanter vacuum integrity check process and apparatus An ion implanter vacuum integrity check process and apparatus that enables a vacuum integrity check at a pressure substantially below the ion implantation process pressure, while storing an ion implantation process pressure set point for a subsequent ion ... | 01/08/2002 |
| 6326664 | Transistor with ultra shallow tip and method of fabrication A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip comprising an ultra shallow region which extends beneath the gate electrode ... | 12/04/2001 |
| 6291303 | Method for manufacturing a bipolar junction device A method of forming an improved bipolar junction device structure. By forming a well region around the emitter terminal, the area of distribution of ions within the emitter terminal of a vertical bipolar junction transistor is enlarged. Furthermore, by fo... | 09/18/2001 |
| 6265277 | Method for making a bipolar transistor for the protection of an integrated circuit against electrostatic discharges In a method for the making of a lateral bipolar transistor, the formation of a field oxide layer on the surface of the substrate, between the collector and the emitter of the protection transistor, is avoided. The lateral bipolar transistors made by the d... | 07/24/2001 |
| 6216099 | Test system and methodology to improve stacked NAND gate based critical path performance and reliability A test system and methodology to improve the performance and reliability of critical paths including stacked NAND gates with sub-minimum channel transistors employs one or more inverter based ring oscillators to generate reliability data. The reliability ... | 04/10/2001 |
| 6174779 | Method for manufacturing a lateral bipolar transistor In a lateral bipolar transistor, its emitter region, base region, link base region, and so forth, are made in self alignment with side walls of masks by using partly overlapping two mask patterns. Therefore, not relying on the mask alignment accuracy, the... | 01/16/2001 |
| 6165860 | Semiconductor device with reduced photolithography steps There is provided a method of fabricating a semiconductor device, including the steps of, in sequence, (a) partially forming a buried layer in a semiconductor substrate and also forming an epitaxial layer on the buried layer, (b) forming a collector regio... | 12/26/2000 |
| 6033964 | System for enhancing the performance of a circuit by reducing the channel length of one or more transistors Generally, decreasing the length of the channel in a CMOS transistor increases the speed of the transistor. However, the degree that the channel can be minimized is limited due to Hot Carrier Injection ("HCI"), which is related to the drain to source volt... | 03/07/2000 |
| 6001770 | Slipping layer for dye-donor element used in thermal dye transfer A dye-donor element for thermal dye transfer comprising a support having on one side thereof a dye layer and on the other side a slipping layer comprising a binder containing polyalkylsilsesquioxane particles wherein less than about 8% of the particles ha... | 12/14/1999 |
| 5885880 | Bipolar transistor device and method for manufacturing the same A semiconductor device is provided in which a vertical NPN transistor and a vertical PNP transistor electrically isolated from each other are formed on a p-type semiconductor substrate. An n-type buried separating region of the vertical PNP transistor is ... | 03/23/1999 |
| 5591656 | Semiconductor integrated circuit device with self-aligned superhigh speed bipolar transistor A superhigh speed vertical transistor having an ultra thin base, a vertical NPN transistor having a reverse direction structure for composing an IIL, and a lateral PNP transistor similarly composing an IIL to be an injector are formed on a P-type silicon ... | 01/07/1997 |
| 5254486 | Method for forming PNP and NPN bipolar transistors in the same substrate In one embodiment, this method forms PNP and NPN transistors in a same epitaxial layer. The P-type regions for both the PNP and the NPN transistors are initially defined using a single masking step. Therefore, the emitter and collector region pattern for ... | 10/19/1993 |
| 5248624 | Method of making isolated vertical PNP transistor in a complementary BICMOS process with EEPROM memory A method and apparatus for an improved isolated vertical PNP in a complementary BICMOS process with EEPROM memory is provided. The isolated vertical PNP transistor is formed on a P-substrate with a P-epitaxial (EPI) layer. The collector of the vertical PN... | 09/28/1993 |
| 4996164 | Method for forming lateral PNP transistor A process of forming a lateral PNP transistor includes the steps of: providing a chip of semiconductor material including an isolated N- device region; implanting N dopant material at a relatively low power and low dosage into a selected implant region of... | 02/26/1991 |
| 4978630 | Fabrication method of bipolar transistor Present invention relates to the fabrication method of the bipolar transistor which includes NPN transistor and field-plate lateral PNP transistor. The arsenic implanted polycrystalline silicon is used for the emitter electrode of NPN transistor to increa... | 12/18/1990 |
| 4743565 | Lateral device structures using self-aligned fabrication techniques Submicron lateral device structures, such as bipolar transistors, Schottky Barrier diodes and resistors, are made using self-aligned fabrication techniques and conventional photolithography. The devices are made using individual submicron silicon protrusi... | 05/10/1988 |
| 4704786 | Method of forming a lateral bipolar transistor in a groove A lateral bipolar transistor is described incorporating at least two grooves extending from the upper surface and spaced apart by a predetermined amount from which impurities are introduced to form an emitter region extending from the sidewall of one groo... | 11/10/1987 |
