Class 438/326 - Including additional electrical device

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process for making complementary bipolar transistors having
No. of patents: 44
Last issue date: 07/21/2009

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Number	Title	Issue Date
7563684	Process for manufacturing an array of cells including selection bipolar junction transistors A process for manufacturing an array of cells, including: implanting, in a body of semiconductor material of a first conductivity type, a common conduction region of the first conductivity type; forming, in the body, above the common conduction region, a plurality o...	07/21/2009
7242071	Semiconductor structure A structure comprises a deep sub-collector buried in a first epitaxial layer and a near sub-collector buried in a second epitaxial layer. The structure further comprises a deep trench isolation structure isolating a region which is substantially above the deep sub-c...	07/10/2007
7164174	Single poly-emitter PNP using dwell diffusion in a BiCMOS technology A method of forming a bipolar transistor device, and more particularly a vertical poly-emitter PNP transistor, as part of a BiCMOS type manufacturing process is disclosed. The formation of the PNP transistor during a CMOS/DMOS fabrication process requires merely one...	01/16/2007
7064416	Semiconductor device and method having multiple subcollectors formed on a common wafer A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors...	06/20/2006
7029981	Radiation hardened bipolar junction transistor A method of forming bipolar junction devices, including forming a mask to expose the total surface of the emitter region and adjoining portions of the surface of the base region. A first dielectric layer is formed over the exposed surfaces. A field plate layer is fo...	04/18/2006
6943428	Semiconductor device including bipolar transistor and buried conductive region A semiconductor device and a method for manufacturing the device using a semiconductor substrate of a high resistance with improved Q value of a passive circuit element. Leakage current due to an impurity fluctuation, in the high resistance semiconductor substrate a...	09/13/2005
6815305	Method for fabricating BICMOS semiconductor devices A method for fabricating a semiconductor device is described in which isolation layers and a collector of a BJT are simultaneously formed by an epitaxtial growth process during a process of fabricating a BiCMOS. The method for fabricating a semiconductor device of t...	11/09/2004
6746928	Method for opening a semiconductor region for fabricating an HBT According to one disclosed embodiment, a transistor gate is fabricated on a substrate. For example, the gate can be a polycrystalline silicon gate in a FET. Thereafter, a conformal layer is deposited over the substrate and the gate and is then etched back to form sp...	06/08/2004
6703657	DRAM cell having electrode with protection layer A DRAM cell is provided, along with a method for fabricating such a DRAM cell. A protection layer pattern is formed to cover a common drain region of first and second access transistors. Storage node holes are then formed to expose each source region of t...	03/09/2004
6551890	Method of manufacturing a semiconductor device comprising a bipolar transistor and a capacitor A method of manufacturing a semiconductor device comprising a poly-emitter transistor (1) and a capacitor (2). A base electrode (14), a first electrode (16, 37) and an emitter window (18) are formed at the same time in a first polysilicon layer (13) cover...	04/22/2003
6297119	Semiconductor device and its manufacture The present invention discloses a semiconductor device having a PNP bipolar transistor and an NPN bipolar transistor having excellent transistor characteristics formed on the same semiconductor substrate, and a method of manufacturing the semiconductor de...	10/02/2001
6184100	Method of manufacturing a photodiode In a light receiving element and a semiconductor device manufacturing method, the low density PN junction is formed by constructing the internal composition of the photodiode with N+ type diffusion layer, N- type epitaxial layer, P	02/06/2001
6146957	Method of manufacturing a semiconductor device having a buried region with higher impurity concentration Since the PN junction of a photodiode is formed of a silicon substrate having a low impurity concentration and an epitaxial layer, the width of the depletion layer in the PN junction is formed wider, the parasitic capacitance by the junction capacitance i...	11/14/2000
5915186	Method of manufacturing heterojunction bipolar device having Si_1-x Ge_x base In a semiconductor device manufacturing method for forming first and second bipolar transistors on a semiconductor substrate 1, a link base layer 5 for connecting a graft base layer (graft base layer 8) of the first bipolar transistor and an intrinsic bas...	06/22/1999
5869381	RF power transistor having improved stability and gain Increased gain and improved stability are realized in using resistive emitter ballasting by including integrated capacitive elements in parallel with the resistive elements in the emitter circuit. A feature of the invention is an integrated capacitor stru...	02/09/1999
5716887	Method of manufacturing BiCMOS device A semiconductor device and a method for manufacturing such a device are presented. The type of semiconductor device is one which merges one type of transistor (e.g., bipolar junction transistors) with another type (e.g., CMOS transistors). Specifically, t...	02/10/1998
5652153	Method of making JFET structures for semiconductor devices with complementary bipolar transistors A semiconductor device may include complementary NPN and PNP transistors and a JFET that is formed in the same steps as used to form the transistors. The bottom gate of the JFET and the back collector layer of the PNP transistor are doped and up-diffused ...	07/29/1997
5591656	Semiconductor integrated circuit device with self-aligned superhigh speed bipolar transistor A superhigh speed vertical transistor having an ultra thin base, a vertical NPN transistor having a reverse direction structure for composing an IIL, and a lateral PNP transistor similarly composing an IIL to be an injector are formed on a P-type silicon ...	01/07/1997
5344785	Method of forming high speed, high voltage fully isolated bipolar transistors on a SOI substrate A method of manufacturing various types of silicon devices, such as complementary bipolar PNP and NPN transistors, in a Silicon On Insulator ("SOI") Integrated Circuit ("IC"), the SOI IC having a substrate, a buried insulating layer disposed above the sub...	09/06/1994
5316964	Method of forming integrated circuits with diffused resistors in isolation regions An integrated circuit having diffused resistors formed in a low impurity concentration isolation region....	05/31/1994
5248624	Method of making isolated vertical PNP transistor in a complementary BICMOS process with EEPROM memory A method and apparatus for an improved isolated vertical PNP in a complementary BICMOS process with EEPROM memory is provided. The isolated vertical PNP transistor is formed on a P-substrate with a P-epitaxial (EPI) layer. The collector of the vertical PN...	09/28/1993
5206182	Trench isolation process A trench isolation process for bipolar and/or MOS circuits employs trench isolation with the trenches extending from an isolation region just below the surface down to and through a buried layer having the same dopant polarity as the isolation regions, so...	04/27/1993
5169794	Method of fabrication of pnp structure in a common substrate containing npn or MOS structures A pnp device in BiCMOS structure (1). PNP transistors (4) are fabricated without the need for additional process steps on the same substrate as npn (2), PMOS (8), and NMOS (6) devices. The process not only requires a minimum number of additional process s...	12/08/1992
5164326	Complementary bipolar and CMOS on SOI A method for fabricating BiCMOS on SOI. An SOI wafer (14) with an oxide layer (17) and a nitride layer (16) has areas isolated by a LOCOS or mesa isolation (13). A region (15) is defined for CMOS structures from which the insulating layers (17,16) are rem...	11/17/1992
5132234	Method of producing a bipolar CMOS device A method of producing a bipolar CMOS device for providing a unipolar CMOS transistor with a polysilicon gate and a self-aligned NPN and VPNP transistor on a same chip, so that a high performance analog and digital BiCMOS device can be realized....	07/21/1992
5066602	Method of making semiconductor IC including polar transistors In a semiconductor IC, a vertical pnp or npn transistor of a uniform characteristic and a high breakdown voltage is made by forming, for example, a p- -collector region (39) in an n-type epitaxial region, an n-well base region (41) formed in th...	11/19/1991
5011784	Method of making a complementary BiCMOS process with isolated vertical PNP transistors A BiCMOS process which provides both isolated and vertical NPN and PNP transistors with better performance characteristics and fewer additional steps than the prior art. The additional steps consist of masked implants with no changes in the thermal steps ...	04/30/1991
4956305	Process for fabricating an integrated circuit The invention relates to a pnp lateral transistor comprised of two regions of p-type conductivity which are incorporated into the surface of a semiconductor area of n-type conductivity and constitute the emitter and collector regions. The portion of the s...	09/11/1990
4826780	Method of making bipolar transistors In a semiconductor IC, a vertical pnp or npn transistor of a uniform characteristic and a high breakdown voltage is made by forming, for example, a p- -collector region (39) in an n-type epitaxial region, an n-well base region (41) formed in th...	05/02/1989
4808547	Method of fabrication of high voltage IC bopolar transistors operable to BV_CBO A high voltage bipolar and JFET have their gate and base connected and source and collector connected and the appropriate geometry for the bipolar to operate to its BVCBO limit. The collector and channel regions have the same depth and impurity...	02/28/1989
4717680	Fabrication of vertical NPN and PNP bipolar transistors in monolithic substrate Vertical PNP and the NPN transistors, each having a gain-bandwidth product greater than 1 GHz are formed in dielectrically isolated regions in polysilicon substrate. The substrate may include additionally dielectrically isolated regions for other devices ...	01/05/1988
4567644	Method of making triple diffused ISL structure An ISL structure is fabricated by a process in which impurities are introduced into a semiconductor substrate (10) of first type conductivity (P) to form major and minor portions (18 and 18a) of a first region of opposite second type conductivity (N). The...	02/04/1986
4550491	Method of making substrate injection logic operator structure An SFL operator and process for its manufacture. The operator is manufactured from a low-doped P-type substrate on which are successively implanted a highly-doped P-type layer and a highly-doped N-type layer. Below a metallic collector contact of the NPN ...	11/05/1985
4510676	Method of fabricating a lateral PNP transistor A method for making a lateral PNP transistor simultaneously with an NPN transistor and the resultant device wherein a first mask defines a base-width by the resistor implant for a P-type resistor and a second mask is overlaid asymmetrically on said first ...	04/16/1985
4505766	Method of fabricating a semiconductor device utilizing simultaneous outdiffusion and epitaxial deposition A semiconductor device has a diffused layer of a first conductivity type which extends to a buried layer of a second conductivity type, formed in a manner to extend from a part of a surface of a semiconductor layer of the second conductivity type which is...	03/19/1985
4476623	Method of fabricating a bipolar dynamic memory cell This describes a novel bipolar dynamic cell array with increased dielectric node capacitance and a method of making it. In the described cell a PNP transistor drives an NPN transistor so that information is stored at the base node capacitance of the PNP t...	10/16/1984
4412376	Fabrication method for vertical PNP structure with Schottky barrier diode emitter utilizing ion implantation A vertical PNP bipolar transistor structure with Schottky Barrier diode emitter is disclosed which simplifies the structure and process steps for combining a complementary PNP in an NPN integrated circuit and improves the speed and density of the vertical...	11/01/1983
4299024	Fabrication of complementary bipolar transistors and CMOS devices with poly gates Specific impurity concentration regions are used for the simultaneous formation of CMOS devices and complementary bipolar transistors to produce high voltage, high performance bipolar transistors. The last diffusion step for shallow P+ and N	11/10/1981
4199860	Method of integrating semiconductor components A dielectric-isolated PNP transistor with Schottky protection, either alone or as one of an integrated pair of complementary bipolar transistors has complete dielectric isolation from neighboring devices and from the substrate by means of a topside anisot...	04/29/1980
4183036	Schottky-transistor-logic A Schottky-transistor-logic arrangement is disclosed which comprises a highly doped semiconductor substrate of one conductivity type. An epitaxial layer of the same conductivity type is formed on the substrate. A deep-implanted doped zone of the other con...	01/08/1980

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Class 438/326 - Including additional electrical device