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| Number | Title | Issue Date |
| 8148228 | Surface patterned topography feature suitable for planarization A method for manufacturing a semiconductor device that comprises implanting a first dopant type in a well region of a substrate to form implanted sub-regions that are separated by non-implanted areas of the well region. The method also comprises forming an oxide lay... | 04/03/2012 |
| 7456069 | Method in the fabrication of an integrated injection logic circuit A method in the fabrication of an I2L circuit comprises (i) forming a common base of a lateral bipolar transistor and emitter of a vertical bipolar multicollector transistor, a common collector of the lateral transistor and base of the vertical multicolle... | 11/25/2008 |
| 7233046 | Semiconductor device and fabrication method thereof A semiconductor device and fabrication method thereof restrains an amplified current between input voltage Vin and ground voltage Vss, and first and second n-wells are biased into internal voltage sources, whereby the current-voltage characteristic of the input pad ... | 06/19/2007 |
| 7192838 | Method of producing complementary SiGe bipolar transistors Method of producing complementary SiGe bipolar transistors. In a method of producing complementary SiGe bipolar transistors, interface oxide layers (38, 58) for NPN and PNP emitters (44, 64), are separately formed and emitter polysilicon (40, 60... | 03/20/2007 |
| 7177454 | Automated detection of objects in a biological sample A method, system, and apparatus are provided for automated light microscopic for detection of proteins associated with cell proliferative disorders. ... | 02/13/2007 |
| 7173320 | High performance lateral bipolar transistor A lateral bipolar transistor includes an emitter region, a base region, a collector region, and a gate disposed over the base region. A bias line is connected to the gate for applying a bias voltage thereto during operation of the transistor. The polarity of the bia... | 02/06/2007 |
| 7133545 | Method and apparatus for automated image analysis of biological specimens A method and apparatus for automated cell analysis of biological specimens automatically scans at a low magnification to acquire images which are analyzed to determine candidate cell objects of interest. The low magnification images are converted from a first color ... | 11/07/2006 |
| 7098113 | Method and system for providing a power lateral PNP transistor using a buried power buss A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer; an emitter region between the first and second collector regions. Therefore slots are placed in each of the regions. Accor... | 08/29/2006 |
| 7099500 | Automated detection of objects in a biological sample A method, system, and apparatus are provided for automated light microscopic for detection of proteins associated with cell proliferative disorders. ... | 08/29/2006 |
| 7095087 | Semiconductor device and fabrication method thereof A semiconductor device and fabrication method thereof restrains an amplified current between input voltage Vin and ground voltage Vss, and first and second n-wells are biased into internal voltage sources, whereby the current-voltage characteristic of the input pad ... | 08/22/2006 |
| 7084485 | Method of manufacturing a semiconductor component, and semiconductor component formed thereby A method of manufacturing a semiconductor component includes: providing a semiconductor substrate (210, 510); forming a trench (130, 430) in the semiconductor substrate to define a plurality of active areas separated from each other by the trench; form... | 08/01/2006 |
| 7061031 | High-sensitivity image sensor and fabrication method thereof A method of fabricating a high-sensitivity image sensor is disclosed. The disclosed method comprises: etching a predetermined region of active silicon and a buried oxide layer by using a mask over an SOI substrate to expose an N-type silicon substrate; implanting P-... | 06/13/2006 |
| 7026221 | Method of forming semiconductor device with bipolar transistor having lateral structure A method of forming a semiconductor device, including forming first and second semiconductor layers of first conductivity type each disposed in a transistor forming region spaced apart from each other by a predetermined distance, so that the first semiconductor laye... | 04/11/2006 |
| 6972237 | Lateral heterojunction bipolar transistor and method of manufacture using selective epitaxial growth A method for manufacturing a heterojunction bipolar transistor is provided. An intrinsic collector structure is formed on a substrate. An extrinsic base structure partially overlaps the intrinsic collector structure. An intrinsic base structure is formed adjacent th... | 12/06/2005 |
| 6919615 | Semiconductor device for integrated injection logic cell and process for fabricating the same A semiconductor device for an integrated injection logic cell having a pnp bipolar transistor structure formed on a semiconductor substrate, wherein at least one layer of insulating films formed on a base region of the pnp bipolar transistor structure is comprised o... | 07/19/2005 |
| 6911715 | Bipolar transistors and methods of manufacturing the same A bipolar transistor in which the occurrence of Kirk effect is suppressed when a high current is injected into the bipolar transistor and a method of fabricating the bipolar transistor are described. The bipolar transistor includes a first collector region of a firs... | 06/28/2005 |
| 6861325 | Methods for fabricating CMOS-compatible lateral bipolar junction transistors A method for fabricating a lateral bipolar junction transistor in an active area of a substrate includes forming a base structure directly on a central portion of the active area without a gate oxide layer being formed on the substrate. The method also includes impl... | 03/01/2005 |
| 6835628 | Integrated circuit with a MOS capacitor The present invention relates to an integrated circuit having a MOS capacitor. In one embodiment, a method of forming an integrated circuit comprises forming an oxide layer on a surface of a substrate, the substrate having a plurality of isolation islands. Each isol... | 12/28/2004 |
| 6803259 | Silicon controlled rectifier for sige process, manufacturing method thereof and integrated circuit including the same A silicon controlled rectifier for SiGe process. The silicon controlled rectifier comprises a substrate, a buried layer of a first conductivity type in the substrate, a well of the first conductivity type in the substrate and above the buried layer, a doped region o... | 10/12/2004 |
| 6790722 | Logic SOI structure, process and application for vertical bipolar transistor A method and structure for forming an emitter in a vertical bipolar transistor includes providing a substrate having a collector layer and a base layer over the collector layer, forming a patterning mask over the collector layer, and filling openings in the mask wit... | 09/14/2004 |
| 6784065 | Bipolar transistor with ultra small self-aligned polysilicon emitter and method of forming the transistor A low-power bipolar transistor is formed to have an intrinsic emitter region with a sub-lithographic width, and an oxide layer that is self aligned to an overlying extrinsic emitter. The small extrinsic emitter region reduces the maximum current that can flow throug... | 08/31/2004 |
| 6782526 | Photomask designing method, a photomask designing apparatus, a computer readable storage medium, a photomask, a photoresist, photosensitive resin, a base plate, a microlens, and an optical element A photomask designing method and apparatus, a computer readable storing medium, a photomask, a photoresist, a photosensitive resin, a base plate, a microlens, and an optical element. In the method, even though a desired depth of a photoresist pattern and a type of t... | 08/24/2004 |
| 6767842 | Implementation of Si-Ge HBT with CMOS process A semiconductor device wherein Si—Ge is the base of a bipolar transistor and a Silicon layer is the emitter. A method of making such a semiconductor device including steps of forming a Silicon dioxide layer on a Silicon substrate, using a photo resist application ... | 07/27/2004 |
| 6759262 | Image sensor with pixel isolation system and manufacturing method therefor An image sensor and method of manufacture therefor includes a substrate having pixel control circuitry. Dielectric layers on the substrate include interconnects in contact with the pixel control circuitry and with pixel electrodes. An intrinsic layer is over the pix... | 07/06/2004 |
| 6596600 | Integrated injection logic semiconductor device and method of fabricating the same A logic circuit is formed of an I2 L cell structure in which a difference of switching speeds at every collectors in a multi-collector structure is small. In a semiconductor device in which an integrated injection logic cell including a constan... | 07/22/2003 |
| 6593628 | Semiconductor device and method of manufacturing same The invention relates to an essentially discrete semiconductor device comprising a semiconductor body (10) having a first, preferably bipolar, transistor (T1) with a first region (1) forming a collector (1) of T1, and a second, preferably also bipolar, tr... | 07/15/2003 |
| 6573146 | Methods of manufacturing complementary bipolar transistors A complementary bipolar transistor having a lateral npn bipolar transistor, a vertical and a lateral pnp bipolar transistor, an integrated injection logic, a diffusion capacitor, a polysilicon capacitor and polysilicon resistors are disclosed. The lateral... | 06/03/2003 |
| 6551869 | Lateral PNP and method of manufacture A lateral PNP is disclosed in which a substrate of a first conductivity type is used. On top of the substrate a buried region of a second conductivity type is formed. A lightly doped collector region is located above the buried region. The lateral PNP als... | 04/22/2003 |
| 6501152 | Advanced lateral PNP by implant negation A lateral NPN transistor (LPNP) (102) having the lightly doped drain extension implant blocked from the emitter region (118) but not the collector region (120). Accordingly, the emitter region (118) has a more abrupt junction for high emitter injection ef... | 12/31/2002 |
| 6489211 | Method of manufacturing a semiconductor component A method of manufacturing a semiconductor component includes providing a composite substrate (300) with a dielectric portion and a semiconductor portion and growing an epitaxial layer (400) over the composite substrate. The epitaxial layer has a polycryst... | 12/03/2002 |
| 6395610 | Method of making bipolar transistor semiconductor device including graded, grown, high quality oxide layer A bipolar transistor includes an oxide layer having graded portions with greatly reduced stress on a silicon substrate. The method of making the oxide preferably includes growing a first oxide portion by upwardly ramping the silicon substrate to a first t... | 05/28/2002 |
| 6232193 | Method of forming isolated integrated injection logic gate An integrated injection logic device is provided in which each collector of an I2L gate is isolated by a field oxide ("FOX"), or by other suitable isolation such as, for example, an isolation trench. The connection of the base to the collectors, between t... | 05/15/2001 |
| 6162695 | Field ring to improve the breakdown voltage for a high voltage bipolar device A method for fabricating a buried layer pinched collector bipolar, (BPCB), device, sharing several process steps with simultaneously formed CMOS devices, has been developed. The BPCB device fabrication sequence features the use of field ring regions, plac... | 12/19/2000 |
| 6146956 | PNP lateral bipolar electronic device and corresponding manufacturing process The invention relates to a process for making a lateral PNP bipolar electronic device integrated monolithically on a semiconductor substrate together with other bipolar devices of the NPN type, said device being incorporated to an electrically insulated m... | 11/14/2000 |
| 6140194 | Method relating to the manufacture of a semiconductor component A manufacturing method for semiconductor components is disclosed which will allow better precision in the definition of the doped areas of the components and the separation of differently doped areas. A selectively shaped area of, for example, polysilicon... | 10/31/2000 |
| 6051873 | Semiconductor device including self-aligned base and emitter electrodes An oxide film mask 6b of a desired shape is formed on the surface of a polysilicon film 5a which becomes a base electrode and the top of the polysilicon film 5a is isotropically etched with the mask 6b, then the polysilicon film 5a is anisotropically etch... | 04/18/2000 |
| 5915186 | Method of manufacturing heterojunction bipolar device having Si1-x Gex base In a semiconductor device manufacturing method for forming first and second bipolar transistors on a semiconductor substrate 1, a link base layer 5 for connecting a graft base layer (graft base layer 8) of the first bipolar transistor and an intrinsic bas... | 06/22/1999 |
| 5693543 | Method of manufacturing a semiconductor IIL device with dielectric and diffusion isolation n type epitaxial layers are formed on the main surface of a p type semiconductor substrate. A field oxide film is selectively formed in the surface of n type epitaxial layers. An n type diffusion region is formed in n type epitaxial layers positioned dire... | 12/02/1997 |
| 5340754 | Method for forming a transistor having a dynamic connection between a substrate and a channel region A vertically raised transistor (10) is formed having a substrate (12). A conductive plug region (22) is selectively or epitaxially formed to vertically elevate the transistor (10). A first doped region (16a) and a second doped region (16b) are each electr... | 08/23/1994 |
| 5240865 | Method of forming a thyristor on an SOI substrate A thyristor (38) is formed over an insulating layer (44). A gate (70) is operable to create a depletion region through the semiconductor layer (46) in which the thyristor (38) is implemented in order to turn the thyristor off. Isolation regions (48, 52) p... | 08/31/1993 |
