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| Number | Title | Issue Date |
| 7271070 | Method for producing transistors The invention relates to a method for producing integrable semiconductor components, especially transistors or logic gates, using a p-doped semiconductor substrate. First of all, a mask is applied to the semiconductor substrate in order to define a window that is de... | 09/18/2007 |
| 7232713 | Methods of forming interconnect lines In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally s... | 06/19/2007 |
| 6960816 | System and method for sensing a magnetic field A magnetic field sensor includes a transistor device having a base region, an emitter region, and a collector region. A barrier region disposed between the emitter region and the collector region to hamper charge carriers injected into the base region from the emitt... | 11/01/2005 |
| 6951790 | Method of forming select lines for NAND memory devices Methods and apparatus are provided. A NAND memory array has a select line coupled to each of a plurality of NAND strings of memory cells of the memory array. The select line has a select gate at each intersection of one of the plurality of NAND strings and the selec... | 10/04/2005 |
| 6911964 | Frame buffer pixel circuit for liquid crystal display An enhanced frame buffer pixel circuit with two control transistors and a separate capacitor put in as a memory capacitor before the memory transistor yields a high contrast ratio by removing induced charge and solving a charge sharing problem between the memory cap... | 06/28/2005 |
| 6815302 | Method of making a bipolar transistor with an oxygen implanted emitter window The present invention provides a method of manufacturing a bipolar transistor. The method may comprise forming a collector in a semiconductor wafer substrate, forming a base in the collector, implanting an oxide region within said collector and over the base, and fo... | 11/09/2004 |
| 6440811 | Method of fabricating a poly-poly capacitor with a SiGe BiCMOS integration scheme A method for fabricating a poly-poly capacitor integrated with a BiCMOS process which includes forming a lower plate electrode of a poly-poly capacitor during deposition of a gate electrode of a CMOS transistor; and forming an upper SiGe plate electrode d... | 08/27/2002 |
| 6323097 | Electrical overlay/spacing monitor method using a ladder resistor A method and structure is disclosed to measure spacing and misalignment of features in semiconductor integrated circuits. Three equally spaced, parallel first level conductive lines are formed on a first insulating layer with staircase patterns projecting... | 11/27/2001 |
| 6303419 | Method for fabricating a BiCMOS device featuring twin wells and an N type epitaxial layer A process for fabricating a BiCMOS device, on a semiconductor substrate, featuring PFET and NFET devices, and an NPN bipolar junction transistor, has been developed. The process features the integration, or the sharing of process steps, used for both the ... | 10/16/2001 |
| 6294431 | Process of manufacture of a non-volatile memory with electric continuity of the common source lines A process for the manufacture of a non-volatile memory with memory cells arranged in word lines and columns in a matrix structure, with source lines extending parallel and intercalate to said lines, said source lines formed by active regions intercalated ... | 09/25/2001 |
| 6232193 | Method of forming isolated integrated injection logic gate An integrated injection logic device is provided in which each collector of an I2L gate is isolated by a field oxide ("FOX"), or by other suitable isolation such as, for example, an isolation trench. The connection of the base to the collectors, between t... | 05/15/2001 |
| 6225179 | Semiconductor integrated bi-MOS circuit having isolating regions different in thickness between bipolar area and MOS area and process of fabrication thereof A bi-MOS circuit is fabricated on first active regions assigned to the bipolar transistor and on second active regions assigned to the field effect transistors, and the field effect transistors are fabricated after said bipolar transistor, because a high-... | 05/01/2001 |
| 6162695 | Field ring to improve the breakdown voltage for a high voltage bipolar device A method for fabricating a buried layer pinched collector bipolar, (BPCB), device, sharing several process steps with simultaneously formed CMOS devices, has been developed. The BPCB device fabrication sequence features the use of field ring regions, plac... | 12/19/2000 |
| 6022778 | Process for the manufacturing of integrated circuits comprising low-voltage and high-voltage DMOS-technology power devices and non-volatile memory cells A process for the manufacturing of an integrated circuit having DMOS-technology power devices and non-volatile memory cells provides for forming respective laterally displaced isolated semiconductor regions, electrically insulated from each other and from... | 02/08/2000 |
| 5915186 | Method of manufacturing heterojunction bipolar device having Si1-x Gex base In a semiconductor device manufacturing method for forming first and second bipolar transistors on a semiconductor substrate 1, a link base layer 5 for connecting a graft base layer (graft base layer 8) of the first bipolar transistor and an intrinsic bas... | 06/22/1999 |
| 5869381 | RF power transistor having improved stability and gain Increased gain and improved stability are realized in using resistive emitter ballasting by including integrated capacitive elements in parallel with the resistive elements in the emitter circuit. A feature of the invention is an integrated capacitor stru... | 02/09/1999 |
| 5770490 | Method for producing dual work function CMOS device A dual work function CMOS device and method for producing the same is disclosed. The method includes: depositing a first layer of a doped material, either n-type or p-type, over a substrate to be doped; defining the areas that are to be oppositely doped; ... | 06/23/1998 |
| 5755979 | Application of semiconductor IC fabrication techniques to the manufacturing of a conditioning head for pad conditioning during chemical-mechanical polish A pad conditioning method and apparatus for chemical-mechanical polishing. A polishing pad (114) is attached to a platen (112) and used to polish a wafer (116). Rotating arm (118) positions the wafer (116) over the pad (114) and applies pressure. During w... | 05/26/1998 |
| 5661066 | Semiconductor integrated circuit In an integrated circuit comprising an IIL and a high frequency npn bipolar transistor which has a deep p- -type base region 45 for its inverted npn output transistors, circuit elements such as a resistor part R, a capacitor part C, a diode par... | 08/26/1997 |
| 5591656 | Semiconductor integrated circuit device with self-aligned superhigh speed bipolar transistor A superhigh speed vertical transistor having an ultra thin base, a vertical NPN transistor having a reverse direction structure for composing an IIL, and a lateral PNP transistor similarly composing an IIL to be an injector are formed on a P-type silicon ... | 01/07/1997 |
| 5166094 | Method of fabricating a base-coupled transistor logic A base-coupled logic gate is characterized by input Schottky diodes that are directly formed on the base region of the switching transistor for the gate. A logic of this type provides flexible circuit arrangements and savings in required area, while achie... | 11/24/1992 |
| 5162252 | Method of fabricating IIL and vertical complementary bipolar transistors The present invention provides a semiconductor device, in particular, a semiconductor device comprising a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same one-conductivity type semiconductor substrate (1). The... | 11/10/1992 |
| 5100810 | Manufacturing method of semiconductor devices On the surface of an insulating substrate, a semi-conductor layer composed of a semiconductor layer of a first conductivity type on which a high-concentration semiconductor layer of the first conductivity type is formed. By selectively etching the semicon... | 03/31/1992 |
| 5066602 | Method of making semiconductor IC including polar transistors In a semiconductor IC, a vertical pnp or npn transistor of a uniform characteristic and a high breakdown voltage is made by forming, for example, a p- -collector region (39) in an n-type epitaxial region, an n-well base region (41) formed in th... | 11/19/1991 |
| 4981807 | Process for fabricating complementary vertical transistor memory cell A compact complementary transistor switch (CTS) memory cell structure utilizing both vertical PNP and vertical NPN transistors in gallium arsenide technology is described. The base region of the vertical PNP transistor merges with the collector region of ... | 01/01/1991 |
| 4567644 | Method of making triple diffused ISL structure An ISL structure is fabricated by a process in which impurities are introduced into a semiconductor substrate (10) of first type conductivity (P) to form major and minor portions (18 and 18a) of a first region of opposite second type conductivity (N). The... | 02/04/1986 |
| 4567501 | Resistor structure in integrated injection logic An I2 L semiconductor device in which a p-type buried layer is formed on an n+ type silicon substrate by diffusion of boron, an epitaxial n-type layer is grown on the p-type buried layer, a p+ type region is formed in a ... | 01/28/1986 |
| 4546539 | I2 L Structure and fabrication process compatible with high voltage bipolar transistors An integrated circuit wherein the base and surface collector regions of the I2 L vertical transistor are formed by the same steps used to form the collector and base, respectively, of complementary bipolar transistors. Thus, a high voltage bipo... | 10/15/1985 |
| 4539742 | Semiconductor device and method for manufacturing the same A semiconductor device wherein collector connecting wiring made of for example n+ -type polycrystalline silicon layer is formed by an anisotropic etching which simultaneously engrave a groove in a semiconductor substrate. A collector layer is f... | 09/10/1985 |
| 4510676 | Method of fabricating a lateral PNP transistor A method for making a lateral PNP transistor simultaneously with an NPN transistor and the resultant device wherein a first mask defines a base-width by the resistor implant for a P-type resistor and a second mask is overlaid asymmetrically on said first ... | 04/16/1985 |
| 4505766 | Method of fabricating a semiconductor device utilizing simultaneous outdiffusion and epitaxial deposition A semiconductor device has a diffused layer of a first conductivity type which extends to a buried layer of a second conductivity type, formed in a manner to extend from a part of a surface of a semiconductor layer of the second conductivity type which is... | 03/19/1985 |
| 4476623 | Method of fabricating a bipolar dynamic memory cell This describes a novel bipolar dynamic cell array with increased dielectric node capacitance and a method of making it. In the described cell a PNP transistor drives an NPN transistor so that information is stored at the base node capacitance of the PNP t... | 10/16/1984 |
| 4475280 | Method of making an integrated circuit incorporating low voltage and high voltage semiconductor devices An integrated circuit incorporating high voltage semiconductor devices which are controlled by low voltage semiconductor devices is disclosed, including a method for making the same. The low voltage devices which are capable of realizing complex logic fun... | 10/09/1984 |
| 4458158 | IC Including small signal and power devices An integrated circuit having first and second N-type epitaxial layers grown over a P-type silicon substrate includes PN junction isolated pockets. In at least one pocket is a small signal device, namely an I2 L transistor. In an adjacent pocket... | 07/03/1984 |
| 4404738 | Method of fabricating an I2 L element and a linear transistor on one chip An integrated circuit device is provided in which an I2 L element and linear transistor are formed on a single chip such that they coexist. In this device, the base and collector regions of a vertical transistor of the I2 L element a... | 09/20/1983 |
| 4338139 | Method of forming Schottky-I2 L devices by implantation and laser bombardment A method for manufacturing a semiconductor device having a Schottky junction which comprises a process for burying first and second regions of a second conductivity type spaced from each other in a semiconductor body of a first conductivity type, a proces... | 07/06/1982 |
| 4272307 | Integrated circuit with I2 L and power transistors and method for making An integrated circuit has a P-type substrate and two N-type epitaxial layers. P-type isolation walls define pockets in the dual-layer epitaxial material, a power transistor being formed in one and an inverted I2 L transistor being formed in ano... | 06/09/1981 |
| 4255209 | Process of fabricating an improved I2 L integrated circuit utilizing diffusion and epitaxial deposition In a complementary pair of bipolar transistors, one vertical and one lateral, the vertical transistor includes a heavily doped buried emitter, lightly doped buried graded base and a heavily doped surface collector and the lateral transistor includes a lig... | 03/10/1981 |
| 4197147 | Method of manufacturing an integrated circuit including an analog circuit and an I2 L circuit utilizing staged diffusion techniques A method of manufacturing an integrated circuit including an analog circuit and an I2 L circuit which both contain NPN transistors on a P-type semiconductor chip in which the method includes an N+ diffusion step for producing a flat ... | 04/08/1980 |
| 4157268 | Localized oxidation enhancement for an integrated injection logic circuit A device and method are disclosed for incorporating on a single semiconductor chip, integrated injection logic (I2 L) circuits operating at low signal voltages and off chip driver devices operating at relatively high signal voltages. The vertic... | 06/05/1979 |
