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| Number | Title | Issue Date |
| 7354779 | Topography compensated film application methods Methods for applying topographically compensated film in a semiconductor wafer fabrication process are disclosed. The processes include premapping a surface of a wafer so as to determine the local topography (e.g., z-height) of the wafer and then applying a variable... | 04/08/2008 |
| 7271070 | Method for producing transistors The invention relates to a method for producing integrable semiconductor components, especially transistors or logic gates, using a p-doped semiconductor substrate. First of all, a mask is applied to the semiconductor substrate in order to define a window that is de... | 09/18/2007 |
| 7221587 | Semiconductor device and programming method The semiconductor device of the present invention includes a column decoder (select and write circuit), which selects multiple pages that are not located adjacently to each other so as to simultaneously program multiple bits in the memory cells of the selected page,... | 05/22/2007 |
| 7144775 | Low-voltage single-layer polysilicon eeprom memory cell The present invention is an electronic memory cell and a method for the cell's fabrication comprising a first transistor configured to be coupled to a bit line. The first transistor has an essentially zero voltage drop when activated and is configured to control an ... | 12/05/2006 |
| 7101750 | Semiconductor device for integrated injection logic cell and process for fabricating the same A semiconductor device for an integrated injection logic cell having a pnp bipolar transistor structure formed on a semiconductor substrate, wherein at least one layer of insulating films formed on a base region of the pnp bipolar transistor structure is comprised o... | 09/05/2006 |
| 7001806 | Semiconductor structure with increased breakdown voltage and method for producing the semiconductor structure A semiconductor structure comprises a buried first semiconductor layer of a first doping type, a second semiconductor layer of the first doping type on the buried semiconductor layer, which is less doped than the buried first semiconductor layer, a semiconductor are... | 02/21/2006 |
| 6980033 | Pseudo CMOS dynamic logic with delayed clocks Structures and methods for pseudo-CMOS dynamic logic with delayed clocks are provided. A pseudo-CMOS dynamic logic circuit with delayed clocks includes a dynamic pseudo-nMOS logic gate and a dynamic pseudo-pMOS logic gate coupled thereto. The dynamic pseudo-nMOS log... | 12/27/2005 |
| 6972599 | Pseudo CMOS dynamic logic with delayed clocks Structures and methods for pseudo-CMOS dynamic logic with delayed clocks are provided. A pseudo-CMOS dynamic logic circuit with delayed clocks includes a dynamic pseudo-nMOS logic gate and a dynamic pseudo-pMOS logic gate coupled thereto. The dynamic pseudo-nMOS log... | 12/06/2005 |
| 6828206 | Semiconductor device and method for fabricating the same In a method for fabricating a semiconductor device, a silicide material is formed at least on the surface of an area to be silicided. Then, a first RTA (Rapid Thermal Annealing) process is performed to form a first-reacted silicide region. Next, a supplemental silic... | 12/07/2004 |
| 6828205 | Method using wet etching to trim a critical dimension A method for using an isotropic wet etching process chemical process for trimming semiconductor feature sizes with improved critical dimension control including providing a hard mask overlying a substrate included in a semiconductor wafer said hard mask patterned fo... | 12/07/2004 |
| 6815302 | Method of making a bipolar transistor with an oxygen implanted emitter window The present invention provides a method of manufacturing a bipolar transistor. The method may comprise forming a collector in a semiconductor wafer substrate, forming a base in the collector, implanting an oxide region within said collector and over the base, and fo... | 11/09/2004 |
| 6797577 | One mask PNP (or NPN) transistor allowing high performance A method is disclosed for the improvement of BiCMOS or CMOS manufactured device performance, specifically bipolar junction transistor performance, in a cost effective manner. The method provides for fewer masking operations during bipolar junction transistor formati... | 09/28/2004 |
| 6596600 | Integrated injection logic semiconductor device and method of fabricating the same A logic circuit is formed of an I2 L cell structure in which a difference of switching speeds at every collectors in a multi-collector structure is small. In a semiconductor device in which an integrated injection logic cell including a constan... | 07/22/2003 |
| 6593628 | Semiconductor device and method of manufacturing same The invention relates to an essentially discrete semiconductor device comprising a semiconductor body (10) having a first, preferably bipolar, transistor (T1) with a first region (1) forming a collector (1) of T1, and a second, preferably also bipolar, tr... | 07/15/2003 |
| 6573146 | Methods of manufacturing complementary bipolar transistors A complementary bipolar transistor having a lateral npn bipolar transistor, a vertical and a lateral pnp bipolar transistor, an integrated injection logic, a diffusion capacitor, a polysilicon capacitor and polysilicon resistors are disclosed. The lateral... | 06/03/2003 |
| 6423603 | Method of forming a microwave array transistor for low-noise and high-power applications A transistor array including a plurality of transistors. Each transistor includes an emitter. An emitter region contact overlies each emitter region. At least one base region underlies each emitter region and is common to a plurality of transistors in the... | 07/23/2002 |
| 6344384 | Method of production of semiconductor device A method of production of a semiconductor device able to be miniaturized by preventing the decline of the hfe at a low current caused by an increase of a surface recombination current of a bipolar transistor and forming the external base region... | 02/05/2002 |
| 6319800 | Static memory cell A static memory cell is described which has cross coupled pulldown transistors and dual access transistors. The memory cell is fabricated such that balanced current paths are formed through the two pulldown transistors. A single word line is used to activ... | 11/20/2001 |
| 6268638 | Metal wire fuse structure with cavity An integrated circuit has primary devices and redundant devices being selective substituted for the primary devices through at least one fuse. The fuse includes a first layer having at least one fuse link region, a second layer over the first layer and ca... | 07/31/2001 |
| 6232193 | Method of forming isolated integrated injection logic gate An integrated injection logic device is provided in which each collector of an I2L gate is isolated by a field oxide ("FOX"), or by other suitable isolation such as, for example, an isolation trench. The connection of the base to the collectors, between t... | 05/15/2001 |
| 6228722 | Method for fabricating self-aligned metal silcide A method of fabricating a self-aligned metal silicide. Two neighboring gates are formed on a substrate, and each of the gates comprises a cap layer thereon. Source/drain regions are formed in the substrate. The source/drain regions comprise a common sourc... | 05/08/2001 |
| 5976940 | Method of making plurality of bipolar transistors In a semiconductor device comprising a first bipolar transistor and a second bipolar transistor having different voltages formed on a semiconductor substrate made by forming an epitaxial layer on a silicon substrate, in an upper part of the silicon substr... | 11/02/1999 |
| 5866461 | Method for forming an integrated emitter switching configuration using bipolar transistors A bipolar power transistor and a low voltage bipolar transistor are combined in an emitter switching or a semibridge configuration in an integrated structure. In a version with non-isolated components, the components of the structure are totally or partia... | 02/02/1999 |
| 5755979 | Application of semiconductor IC fabrication techniques to the manufacturing of a conditioning head for pad conditioning during chemical-mechanical polish A pad conditioning method and apparatus for chemical-mechanical polishing. A polishing pad (114) is attached to a platen (112) and used to polish a wafer (116). Rotating arm (118) positions the wafer (116) over the pad (114) and applies pressure. During w... | 05/26/1998 |
| 4981807 | Process for fabricating complementary vertical transistor memory cell A compact complementary transistor switch (CTS) memory cell structure utilizing both vertical PNP and vertical NPN transistors in gallium arsenide technology is described. The base region of the vertical PNP transistor merges with the collector region of ... | 01/01/1991 |
| 4651410 | Method of fabricating regions of a bipolar microwave integratable transistor A method of fabricating bipolar integratable transistors includes a recrystallization step. A monocrystalline epitaxial layer is deposited upon a highly doped substrate and impurities are introduced into a portion of the epitaxial layer to form a first tr... | 03/24/1987 |
| 4433470 | Method for manufacturing semiconductor device utilizing selective etching and diffusion A method of manufacturing a semiconductor device wherein grooves are formed between vertical type-npn transistors and insulating oxide layers are formed on the bottoms of the grooves, thereby preventing parasitic p-n junctions, which is characterized in t... | 02/28/1984 |
| 4420874 | Method of producing an IIL semiconductor device utilizing self-aligned thickened oxide patterns An I2 L type semiconductor device having an elementary region which is isolated by V-shape grooves from the other portions of the device, said semiconductor device comprising an insulating layer coating covering the surface of the semiconductor... | 12/20/1983 |
| 4408388 | Method for manufacturing a bipolar integrated circuit device with a self-alignment base contact A method for manufacturing a semiconductor integrated circuit device having a plurality of bipolar transistors is characterized in that, using an antioxidant insulation film pattern as a mask, an underlying conductive layer is overetched to form a conduct... | 10/11/1983 |
| 4407059 | Method of producing semiconductor device Disclosed is a method of producing a semiconductor device, comprising forming an oxidation-resistive insulating film having one or more openings on a semiconductor substrate, forming an impurity-doped polysilicon pattern in at least the opening of the ins... | 10/04/1983 |
| 4404737 | Method for manufacturing a semiconductor integrated circuit utilizing polycrystalline silicon deposition, oxidation and etching A method for manufacturing a semiconductor integrated circuit includes diffusing an impurity of a second conductivity type into polycrystalline silicon layers formed on a first conductivity region in a substrate to form second conductivity regions, the po... | 09/20/1983 |
| 4385433 | Method of forming metal silicide interconnection electrodes in I2 L-semiconductor devices An exposed surface of a semiconductor substrate with an integrated injection logic semiconductor region having a first conductivity injector region of which one surface is exposed, a first conductivity type base region of which part of the surface is expo... | 05/31/1983 |
| 4377903 | Method for manufacturing an I2 L semiconductor device An oxide layer is partially formed on an n-type region surrounded by a field oxide region. A base region of a switching transistor is formed in the n-type region using as a mask the oxide layer. Arsenic-doped polysilicon layers are selectively formed simu... | 03/29/1983 |
| 4255209 | Process of fabricating an improved I2 L integrated circuit utilizing diffusion and epitaxial deposition In a complementary pair of bipolar transistors, one vertical and one lateral, the vertical transistor includes a heavily doped buried emitter, lightly doped buried graded base and a heavily doped surface collector and the lateral transistor includes a lig... | 03/10/1981 |
| 4240846 | Method of fabricating up diffused substrate FED logic utilizing a two-step epitaxial deposition A complementary pair of vertically aligned, inversely operated transistors formed from a P type substrate, a first N type epitaxial layer, a second N type epitaxial layer and a buried, updiffused P type region between the two epitaxial layers. The impurit... | 12/23/1980 |
| 4199378 | Method of manufacturing a semiconductor device and semiconductor device manufactured while using such a method A method of manufacturing LOCOS transistors in which base doping, emitter doping and emitter metallization are provided via the same aperture. Problems at the edge of the sunken oxide are eliminated by a two-stage doping technique so that the channel stop... | 04/22/1980 |
| 4170501 | Method of making a semiconductor integrated circuit device utilizing simultaneous outdiffusion and autodoping during epitaxial deposition A semiconductor integrated circuit device includes circuit elements having relatively different performance characteristics in which buried regions having different chemical elements are used to autodope an epitaxial layer to different degrees.... | 10/09/1979 |
| 4148055 | Integrated circuit having complementary bipolar transistors An integrated circuit having two vertical complementary bipolar transistors formed from a semiconductor substrate of a first conductivity type, and a deposited layer of second semiconductor type is disclosed. Conductor tracks consisting of portions of the... | 04/03/1979 |
| 4140559 | Method of fabricating an improved substrate fed logic utilizing graded epitaxial deposition An integrated circuit having a substrate of a first conductivity type, a first layer of opposite conductivity type thereon and a second layer of said first conductivity type inversely graded on said first layer and including a heavily doped region adjacen... | 02/20/1979 |
| 4106049 | Semiconductor device A semiconductor device comprises a D.C. voltage supply region comprising a semiconductor substrate of one conductivity type having a first layer of high impurity concentration at least at its surface, and a second layer of low impurity concentration and o... | 08/08/1978 |
