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| Number | Title | Issue Date |
| 7863148 | Method for integrating SiGe NPN and vertical PNP devices According to one exemplary embodiment, a method for forming an NPN and a vertical PNP device on a substrate comprises forming an insulating layer over an NPN region and a PNP region of the substrate. The method further comprises forming a buffer layer on the insulat... | 01/04/2011 |
| 7442617 | Method for manufacturing bipolar transistor A method for manufacturing a bipolar transistor comprising: forming a device isolation layer in a device isolation region of a semiconductor substrate having therein first and second well regions having a first conductivity; implanting ions of a second conductivity ... | 10/28/2008 |
| 7419611 | Processes and materials for step and flash imprint lithography A method of forming an image. The method includes: a transfer layer on a substrate; forming on the transfer layer, an etch barrier layer; pressing a template having a relief pattern into the etch barrier layer; exposing the etch barrier layer to actinic radiation fo... | 09/02/2008 |
| 7396732 | Formation of deep trench airgaps and related applications A method for forming deep trench or via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), depositing spacers on the sidewalls of the unfille... | 07/08/2008 |
| 7393731 | Semiconductor device and method of manufacturing the same A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure, a semiconductor device comprising an isolation insulating film of PTI structure, which sup... | 07/01/2008 |
| 7348250 | Bipolar structure with two base-emitter junctions in the same circuit Bipolar integrated circuits employing SiGe technology incorporate the provision of mask-selectable types of bipolar transistors. A high-performance/high variability type has a thin base in which the diffusion from the emitter intersects the base dopant diffusion wit... | 03/25/2008 |
| 7347228 | Method of making semiconductor devices A method for fabricating semiconductor device is provided. A high stress layer formed on, under or on both sides of the transistors of the semiconductor device is employed as a cap layer. A specific region is then defined through photo resistor mask, and the stress ... | 03/25/2008 |
| 7329583 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 02/12/2008 |
| 7329584 | Method for manufacturing bipolar transistor A method for manufacturing a bipolar transistor includes: forming a device isolation layer on a semiconductor substrate having first and second well regions of a first conductivity therein; implanting ions of a second conductivity in the first well to form a third w... | 02/12/2008 |
| 7285473 | Method for fabricating low-defect-density changed orientation Si The present invention provides a method for forming low-defect density changed-orientation Si by amorphization/templated recrystallization (ATR) processes in which regions of Si having a first crystal orientation are amorphized by ion implantation and then recrystal... | 10/23/2007 |
| 7285469 | Bipolar method and structure having improved BVCEO/RCS trade-off made with depletable collector columns In accordance with the invention, there are various methods of making an integrated circuit comprising a bipolar transistor. According to an embodiment of the invention, the bipolar transistor can comprise a substrate, a collector comprising a plurality of alternati... | 10/23/2007 |
| 7282401 | Method and apparatus for a self-aligned recessed access device (RAD) transistor gate A method used in fabrication of a recessed access device transistor gate has increased tolerance for mask misalignment. One embodiment of the invention comprises forming a vertical spacing layer over a semiconductor wafer, then etching the vertical spacing layer and... | 10/16/2007 |
| 7279378 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/09/2007 |
| 7279793 | System and method for manufacturing semiconductor devices using an anti-reflective coating layer An anti-reflective coating layer for the manufacturing of semiconductor devices is disclosed. In one example, a partial semiconductor device includes a substrate; a bottom anti-reflective coating (BARC) layer over the substrate, and the BARC layer is transformed fro... | 10/09/2007 |
| 7276431 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/02/2007 |
| 7265010 | High performance vertical PNP transistor method The invention includes a method and resulting structure for fabricating high performance vertical NPN and PNP transistors for use in BiCMOS devices. The resulting high performance vertical PNP transistor includes an emitter region including silicon and germanium, an... | 09/04/2007 |
| 7261919 | Silicon carbide and other films and method of deposition A method of depositing a ceramic film, particularly a silicon carbide film, on a substrate is disclosed in which the residual stress, residual stress gradient, and resistivity are controlled. Also disclosed are substrates having a deposited film with these controlle... | 08/28/2007 |
| 7253480 | Structure and fabrication method of electrostatic discharge protection circuit A structure of an electrostatic discharge protection circuit, in which a buried layer is formed in the substrate of the electrostatic discharge protection circuit, and a sinker layer electrically connected to the buried layer and a drain is also formed therein. Ther... | 08/07/2007 |
| 7226835 | Versatile system for optimizing current gain in bipolar transistor structures Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406 | 06/05/2007 |
| 7217628 | High performance integrated vertical transistors and method of making the same A complementary bipolar transistor is fabricated using an available portion of a silicon germanium (SiGe) low temperature epitaxial layer as the raised base region for a vertical NPN transistor, and another portion of the same SiGe LTE layer as a vertical PNP collec... | 05/15/2007 |
| 7208394 | Method of manufacturing a semiconductor device with a fluorine concentration At present, a forming process of a base film through an amorphous silicon film is conducted in respective film forming chambers in order to obtain satisfactory films. When continuous formation of the base film through the amorphous silicon film is performed in a sin... | 04/24/2007 |
| 7195965 | Premature breakdown in submicron device geometries The concept of the present invention describes a semiconductor device with a junction 504 between a lightly doped region 501 and a heavily doped region 502, wherein the junction has an elongated portion 504a and curved portions ... | 03/27/2007 |
| 7190046 | Bipolar transistor having reduced collector-base capacitance Structure and method are provided for forming a bipolar transistor. As disclosed, an intrinsic base layer is provided overlying a collector layer. A low-capacitance region is disposed laterally adjacent the collector layer. The low-capacitance region includes at lea... | 03/13/2007 |
| 7183576 | Epitaxial and polycrystalline growth of SiGeCand SiCalloy layers on Si by UHV-CVD A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique ... | 02/27/2007 |
| 7166517 | Semiconductor device and method of manufacture thereof The present invention provides a method of manufacturing a semiconductor device which includes an amorphous semiconductor film forming treatment of supplying a starting material gas containing germanium to a semiconductor substrate, thereby forming an amorphous semi... | 01/23/2007 |
| 7135349 | Photodiode and method of fabricating the same Photodiodes and methods of fabricating photodiodes are provided. For example, a method of fabricating a photodiode includes forming a buried layer of a first conductive type on a semiconductor substrate and forming a first intrinsic capping epitaxial layer on the bu... | 11/14/2006 |
| 7067383 | Method of making bipolar transistors and resulting product A method of forming bipolar transistors by using the same mask to form the collector region in a substrate of an opposite conductivity type as to form the base in the collector region. More specifically, impurities of a first conductivity type are introduced into a ... | 06/27/2006 |
| 7064416 | Semiconductor device and method having multiple subcollectors formed on a common wafer A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors... | 06/20/2006 |
| 7041563 | Semiconductor device having a shallow trench isolation and method of fabricating the same The present invention includes a semiconductor device having a shallow trench isolation and a method of fabricating the same. The semiconductor device includes a gate electrode being arranged to cross over the active region. An oxide pattern is interposed between th... | 05/09/2006 |
| 7033920 | Method for fabricating a silicon carbide interconnect for semiconductor components An interconnect for semiconductor components includes a substrate, and interconnect contacts on the substrate for electrically engaging component contacts on the components. The interconnect contacts include silicon carbide conductive layers, and conductors in elect... | 04/25/2006 |
| 7033899 | Method of making semiconductor devices A method for fabricating semiconductor device is provided. A high stress layer formed on, under or on both sides of the transistors of the semiconductor device is employed as a cap layer. A specific region is then defined through photo resistor mask, and the stress ... | 04/25/2006 |
| 7026666 | Self-aligned NPN transistor with raised extrinsic base A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has a raised extrinsic base such that the link base resistance is reduced by providing an extrinsic base which is thicker than the intrinsic base. The increase i... | 04/11/2006 |
| 7001806 | Semiconductor structure with increased breakdown voltage and method for producing the semiconductor structure A semiconductor structure comprises a buried first semiconductor layer of a first doping type, a second semiconductor layer of the first doping type on the buried semiconductor layer, which is less doped than the buried first semiconductor layer, a semiconductor are... | 02/21/2006 |
| 6987039 | Forming lateral bipolar junction transistor in CMOS flow A method of forming a lateral bipolar transistor without added mask in CMOS flow including a p-substrate; patterning and n-well implants; pattern and implant pocket implants for core nMOS and MOS; pattern and implants pocket implants I/O nMOS and pMOS; sidewall depo... | 01/17/2006 |
| 6972237 | Lateral heterojunction bipolar transistor and method of manufacture using selective epitaxial growth A method for manufacturing a heterojunction bipolar transistor is provided. An intrinsic collector structure is formed on a substrate. An extrinsic base structure partially overlaps the intrinsic collector structure. An intrinsic base structure is formed adjacent th... | 12/06/2005 |
| 6972472 | Quasi self-aligned single polysilicon bipolar active device with intentional emitter window undercut An emitter stack for a quasi-self-aligned bipolar (NPN or PNP) transistor is formed where two layers over the emitter of a silicon substrate are windowed in a manner to under cut the top layer thereby exposing the substrate material. The emitter polysilicon structur... | 12/06/2005 |
| 6969665 | Method of forming an isolation film in a semiconductor device Disclosed is a method of forming an isolation film in a semiconductor device. The method comprises the steps of providing a semiconductor substrate having a region where a P well will be formed and a region where a N well will be formed, forming an oxide film and a ... | 11/29/2005 |
| 6962842 | Method of removing a sacrificial emitter feature in a BICMOS process with a super self-aligned BJT A method of removing a sacrificial emitter feature in a bipolar complementary metal oxide semiconductor (BICMOS) process with a super self-aligned bipolar junction transistor (BJT) is disclosed. According to the new method, a mask layer, such as an oxide deposited u... | 11/08/2005 |
| 6936509 | STI pull-down to control SiGe facet growth A SiGe bipolar transistor including a semiconductor substrate having a collector and sub-collector region formed therein, wherein the collector and sub-collector are formed between isolation regions that are also present in the substrate is provided. Each isolation ... | 08/30/2005 |
| 6933202 | Method for integrating SiGe NPN and vertical PNP devices on a substrate and related structure According to one exemplary embodiment, a method for forming an NPN and a vertical PNP device on a substrate comprises forming an insulating layer over an NPN region and a PNP region of the substrate. The method further comprises forming a buffer layer on the insulat... | 08/23/2005 |
