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| Number | Title | Issue Date |
| 7396757 | Interconnect structure with dielectric air gaps An interconnect structure with improved performance and capacitance by providing air gaps inside the dielectric layer by use of a multi-phase photoresist material. The interconnect features are embedded in a dielectric layer having a columnar air gap structure in a ... | 07/08/2008 |
| 7368764 | Heterojunction bipolar transistor and method to make a heterojunction bipolar transistor A heterojunction bipolar transistor and a method of making a heterojunction bipolar transistor. The heterojunction bipolar transistor includes: a regrown emitter region; an intrinsic base region forming a junction with the regrown emitter region; and an extrinsic ba... | 05/06/2008 |
| 7358179 | Method of manufacturing semiconductor device including air space formed around gate electrode After a HEMT is formed, side walls are formed on a semiconductor substrate. Next, a sacrificial layer is formed to cover the HEMT. Next, contact holes are formed in the sacrificial layer to expose upper surfaces of source electrodes. Next, a metal interconnect line ... | 04/15/2008 |
| 7256433 | Bipolar transistor and a method of manufacturing the same A bipolar transistor having enhanced characteristics is fabricated by etching a base mesa, which is formed below an emitter mesa (upper emitter layer) and a base electrode, so as to have jut regions on the edges of its generally rectangular region. A mask film, e.g.... | 08/14/2007 |
| 7217628 | High performance integrated vertical transistors and method of making the same A complementary bipolar transistor is fabricated using an available portion of a silicon germanium (SiGe) low temperature epitaxial layer as the raised base region for a vertical NPN transistor, and another portion of the same SiGe LTE layer as a vertical PNP collec... | 05/15/2007 |
| 7214594 | Method of making semiconductor device using a novel interconnect cladding layer A method and apparatus are provided an interconnect cladding layer. In one embodiment, a first sacrificial layer is deposited over a substrate and patterned. In the vias created during the patterning operation, a conductive material is placed to create conductive in... | 05/08/2007 |
| 7205486 | Thermally isolated via structure This document discusses, among other things, a flexible circuit or other laminate comprising a first conductive layer and a second conductive layer disposed over the first conductive layer. An insulator is disposed between the first and second conductive layers. A c... | 04/17/2007 |
| 7138329 | Air gap for tungsten/aluminum plug applications An air gap structure and formation method for substantially reducing the undesired capacitance between adjacent interconnects, metal lines or other features in an integrated circuit device is disclosed. The air gap extends above, and may also additionally extend bel... | 11/21/2006 |
| 7112866 | Method to form a cross network of air gaps within IMD layer The invention provides a new multilevel interconnect structure of air gaps in a layer of IMD. A first layer of dielectric is provided over a surface; the surface contains metal points of contact. Trenches are provided in this first layer of dielectric. The trenches ... | 09/26/2006 |
| 7109534 | Transistor and electronic device The invention provides a transistor capable of achieving a higher speed although its construction is easy to manufacture without requiring wiring to intersect three-dimensionally even if unit elements of transistors are connected in parallel, and to provide an elect... | 09/19/2006 |
| 7094669 | Structure and method of liner air gap formation A structure and method of a semiconductor device with liner air gaps next to interconnects and dielectric layers. A dielectric layer is formed over a lower dielectric layer and a lower interconnect over a substrate. We form an interconnect opening in the dielectric ... | 08/22/2006 |
| 7067898 | Semiconductor device having a self-aligned base contact and narrow emitter A semiconductor structure having a self-aligned base contact and an emitter, where the base contact is electrically isolated from the emitter by a dielectric layer. The separation between the base contact and the emitter is determined by the thickness of the dielect... | 06/27/2006 |
| 7064361 | NPN transistor having reduced extrinsic base resistance and improved manufacturability According to one exemplary embodiment, an NPN bipolar transistor comprises a base layer situated over a collector, where the base layer comprises an intrinsic base region and an extrinsic base region. The NPN bipolar transistor may be, for example, an NPN silicon-ge... | 06/20/2006 |
| 7064360 | Bipolar transistor and method for fabricating it A method is provided to fabricate a bipolar transistor with a low base connection resistance, low defect density and improved scalability. Scalability is to be understood in this case as both the lateral scaling of the emitter window and the vertical scaling of the ... | 06/20/2006 |
| 7038254 | Hetero-junction bipolar transistor having a transition layer between the base and the collector This invention provides a double hetero-junction bipolar transistor (DHBT) in which a probability of the impact ionization at the interface between the base and the collector is reduced, thereby enhancing the break down voltage. In the present DHBT, a plurality of t... | 05/02/2006 |
| 6998695 | Semiconductor device having a mushroom gate with hollow space A method of manufacturing a semiconductor device has the steps of: forming a mushroom gate traversing an active region of a semiconductor substrate and having a fine gate and an expanded over gate formed thereon; coating a first organic material film on the semicond... | 02/14/2006 |
| 6964907 | Method of etching a lateral trench under an extrinsic base and improved bipolar transistor In a BJT, the extrinsic base to collector capacitance is reduced by forming a lateral trench between the extrinsic base region and collector. This is typically done by using an anisotropic wet etch process in a direction of a orientation wafer. ... | 11/15/2005 |
| 6946355 | Method for producing a hetero-bipolar transistor and hetero-bipolar transistor A hetero-bipolar transistor on Ga—As basis which has an advantageous design and to a method for producing the same which allows production of inexpensive and long-term stable components. ... | 09/20/2005 |
| 6924203 | Double HBT base metal micro-bridge A heterojunction bipolar transistor (HBT) device structure is provided which facilitates the reduction of the base-collector capacitance and a method for making the same. The base-collector capacitance is decreased by fabricating a base micro-bridge connecting a bas... | 08/02/2005 |
| 6924201 | Heterojunction bipolar transistor and method of producing the same A heterojunction bipolar transistor of the present invention is produced from a wafer including a substrate and a collector layer of a first conductivity type, a base layer of a second conductivity type and an emitter layer of the first conductivity type sequentiall... | 08/02/2005 |
| 6906360 | Structure and method of making strained channel CMOS transistors having lattice-mismatched epitaxial extension and source and drain regions A structure and method are provided in which an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET) each have a channel region disposed in a single-crystal layer of a first semiconductor and a stress is applied at a first magnitude to a... | 06/14/2005 |
| 6905929 | Single poly EPROM cell having smaller size and improved data retention compatible with advanced CMOS process Leakage of a single-poly EPROM cell is prevented by eliminating field oxide isolating the source, channel, and drain from the control gate n-well, and by replacing field oxide surrounding the cell with a heavily doped surface isolation region. The EPROM cell also ut... | 06/14/2005 |
| 6890828 | Method for supporting a bond pad in a multilevel interconnect structure and support structure formed thereby A method for forming interlevel dielectric levels in a multilevel interconnect structure formed by a damascene process. The conductive features characteristic of the damascene process are formed in a removable mandrel material for each level of the interconnect stru... | 05/10/2005 |
| 6867079 | Method for manufacturing semiconductor device The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. T... | 03/15/2005 |
| 6730571 | Method to form a cross network of air gaps within IMD layer In accordance with the objectives of the invention a new method is provided for creating air gaps in a layer of IMD. First and second layers of dielectric are successively deposited over a surface; the surface contains metal lines running in an Y-direction. Trenches... | 05/04/2004 |
| 6724055 | Semiconductor structure having an interconnect and method of producing the semiconductor structure The semiconductor structure has an interconnect that is isolated by a cavity from an underlying insulating layer on a support. The fabrication method provides for the interconnect firstly to be patterned on a double layer and to be provided with an insulating coveri... | 04/20/2004 |
| 6645819 | Self-aligned fabrication method for a semiconductor device One embodiment of the present invention provides a method of fabricating a semiconductor device including the steps of forming a first semiconductor layer; forming a second semiconductor layer over the first semiconductor layer; forming a mask over a firs... | 11/11/2003 |
| 6605519 | Method for thin film lift-off processes using lateral extended etching masks and device A method for forming an etching mask structure on a substrate includes etching the substrate, laterally expanding the etching mask structure, and depositing a self-aligned metal layer that is aligned to the originally masked area. The etching can be isotr... | 08/12/2003 |
| 6589848 | Photodetector device and method for manufacturing the same A photodetector device and a process for manufacturing the same are described. The photodetector device comprises a doped semiconductor substrate; an intrinsic semiconductor material layer formed over the substrate, for absorbing incident light; an upper ... | 07/08/2003 |
| 6570217 | Semiconductor device and method of manufacturing the same To provide a cavity in the portion of the silicon substrate which lies beneath the channel region of the MOS transistor.... | 05/27/2003 |
| 6492238 | Bipolar transistor with raised extrinsic base fabricated in an integrated BiCMOS circuit A process for forming a bipolar transistor with a raised extrinsic base, an emitter, and a collector integrated with a CMOS circuit with a gate. An intermediate semiconductor structure is provided having CMOS and bipolar areas. An intrinsic base layer is ... | 12/10/2002 |
| 6472285 | Method for fabricating high-Q inductance device in monolithic technology The present invention provides a high-Q inductance device and a method for fabricating the same. The inductance device is formed on a semiconductor substrate and includes at least one spiral conducting line and a passivation layer formed above the spiral ... | 10/29/2002 |
| 6448177 | Method of making a semiconductor device having a dual damascene interconnect spaced from a support structure A semiconductor device and an improved method for making it are described. The semiconductor device comprises a dual damascene interconnect that includes a conductive line. The device further includes a support structure that is spaced from the conductive... | 09/10/2002 |
| 6426267 | Method for fabricating high-Q inductance device in monolithic technology The present invention provides a method for fabricating a high-Q inductance device. First, a first dielectric layer is formed on a semiconductor substrate. A spiral conducting line is formed above the first dielectric layer. Then, a passivation layer is f... | 07/30/2002 |
| 6406965 | Method of fabricating HBT devices A method of fabricating an HBT transistor with extremely high speed and low operating current. The transistor has a small base area and a small emitter area with most of the emitter area contacted with metal, most of the base area, outside of the emitter,... | 06/18/2002 |
| 6395608 | Heterojunction bipolar transistor and its fabrication method A heterojunction bipolar transistor and its fabrication method is disclosed. The heterojunction bipolar transistor includes a substrate; a collector layer formed to have a ledge or MESA on the substrate; a collector electrode formed on the collector layer... | 05/28/2002 |
| 6297145 | Method of forming a wiring layer having an air bridge construction A method of manufacturing a semiconductor device having a wiring layer with an air bridge construction includes the steps of forming a lower layer metal interconnect, depositing an interlayer insulation film, depositing a first and a second insulation fil... | 10/02/2001 |
| 6251738 | Process for forming a silicon-germanium base of heterojunction bipolar transistor A process for forming a silicon-germanium base of a heterojunction bipolar transistor. First, a silicon substrate having a mesa surrounded by a trench is formed. Next, a silicon-germanium layer is deposited on the substrate and the portion of the silicon-... | 06/26/2001 |
| 6140249 | Low dielectric constant dielectric films and process for making the same A low dielectric constant material and a process for controllably reducing the dielectric constant of a layer of such material is provided and comprises the step of exposing the layer of dielectric material to a concentration of an oxygen plasma at a temp... | 10/31/2000 |
| 6124177 | Method for making deep sub-micron mosfet structures having improved electrical characteristics A method for making improved MOSFET structures is achieved. A Si3 N4 and a SiO2 layer are deposited and patterned to have openings for gate electrodes over device areas on a substrate. A second Si3 N4... | 09/26/2000 |
