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| Number | Title | Issue Date |
| 8110472 | High power and high temperature semiconductor power devices protected by non-uniform ballasted sources A semiconductor power device is formed on a semiconductor substrate. The semiconductor power device includes a plurality of transistor cells distributed over different areas having varying amount of ballasting resistances depending on a local thermal dissipation in ... | 02/07/2012 |
| 7723198 | Integrated semiconductor cascode circuit for high-frequency applications An integrated semiconductor cascode circuit is provided that comprises an emitter layer, a first base area, a second base area, an intermediate area and a collector area. The first base area is arranged between the emitter layer and the intermediate area, and the se... | 05/25/2010 |
| 7482237 | Semiconductor device and method of producing the same, and power conversion apparatus incorporating this semiconductor device The temperature of a bipolar semiconductor element using a wide-gap semiconductor is raised using heating means, such as a heater, to obtain a power semiconductor device being large in controllable current and low in loss. The temperature is set at a temperature hig... | 01/27/2009 |
| 7262484 | Structure and method for performance improvement in vertical bipolar transistors A method of forming a semiconductor device having two different strains therein is provided. The method includes forming a strain in a first region with a first straining film, and forming a second strain in a second region with a second straining film. Either of th... | 08/28/2007 |
| 7256433 | Bipolar transistor and a method of manufacturing the same A bipolar transistor having enhanced characteristics is fabricated by etching a base mesa, which is formed below an emitter mesa (upper emitter layer) and a base electrode, so as to have jut regions on the edges of its generally rectangular region. A mask film, e.g.... | 08/14/2007 |
| 7224005 | Heterojunction bipolar transistor structure A material made by arranging layers of gallium-arsenide-antimonide (GaAsxSb1-x, 0.0≦x≦1.0) and/or indium-gallium-arsenic-nitride (InyGa1-yAszN1-z, 0.0≦y, z≦1.0) in a specific order is used to ... | 05/29/2007 |
| 7208387 | Method for manufacturing compound semiconductor wafer and compound semiconductor device A method for producing a compound semiconductor wafer used for production of HBT by vapor growth of a sub-collector layer, a collector layer, a base layer and an emitter layer in this turn on a compound semiconductor substrate using MOCVD method wherein the base lay... | 04/24/2007 |
| 7192838 | Method of producing complementary SiGe bipolar transistors Method of producing complementary SiGe bipolar transistors. In a method of producing complementary SiGe bipolar transistors, interface oxide layers (38, 58) for NPN and PNP emitters (44, 64), are separately formed and emitter polysilicon (40, 60... | 03/20/2007 |
| 7176098 | Semiconductor element and method for fabricating the same A heterojunction bipolar transistor comprises a collector layer, a base layer formed on the collector layer and an emitter layer formed on the base layer. The emitter layer includes a first semiconductor layer covering the entire top surface of the base layer and a ... | 02/13/2007 |
| 7173274 | Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe bas... | 02/06/2007 |
| 7141481 | Method of fabricating nano-scale resistance cross-point memory array A method of fabricating a nano-scale resistance cross-point memory array includes preparing a silicon substrate; depositing silicon oxide on the substrate to a predetermined thickness; forming a nano-scale trench in the silicon oxide; depositing a first connection l... | 11/28/2006 |
| 7132320 | Method for manufacturing semiconductor device The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. T... | 11/07/2006 |
| 7119382 | Heterobipolar transistor and method of fabricating the same The present invention realizes a heterobipolar transistor using a SiGeC base layer in order to improve its electric characteristics. Specifically, the distribution of carbon and boron within the base layer is controlled so that the concentration of boron is higher t... | 10/10/2006 |
| 7118982 | Emitter and method of making An emitter includes an electron source and a cathode. The cathode has an emissive surface. The emitter further includes a continuous anisotropic conductivity layer disposed between the electron source and the emissive surface of the cathode. The anisotropic conducti... | 10/10/2006 |
| 7091082 | Semiconductor method and device A method for enhancing operation of a bipolar light-emitting transistor includes the following steps: providing a bipolar light-emitting transistor having emitter, base, and collector regions; providing electrodes for coupling electrical signals with the emitter, ba... | 08/15/2006 |
| 7045378 | Forming a photodiode to include a superlattice exclusion layer A photosensitive diode has superlattice exclusion region formed from a stack of first and second layers. The first layers are penetrated by minority carriers using quantum mechanical tunneling and reduce minority carrier mobility. The second layers have a sufficient... | 05/16/2006 |
| 7045401 | Strained silicon finFET device Disclosing is a strained silicon finFET device having a strained silicon fin channel in a double gate finFET structure. The disclosed finFET device is a double gate MOSFET consisting of a silicon fin channel controlled by a self-aligned double gate for suppressing s... | 05/16/2006 |
| 7038254 | Hetero-junction bipolar transistor having a transition layer between the base and the collector This invention provides a double hetero-junction bipolar transistor (DHBT) in which a probability of the impact ionization at the interface between the base and the collector is reduced, thereby enhancing the break down voltage. In the present DHBT, a plurality of t... | 05/02/2006 |
| 7030462 | Heterojunction bipolar transistor having specified lattice constants A Heterojunction Bipolar Transistor, HBT, (100) containing a collector layer (104), a base layer (105) and an emitter layer (106) is constructed such that the collector layer (104), the base layer (105) and the emitter layer... | 04/18/2006 |
| 7005362 | Method of fabricating a thin film transistor A method of fabricating a TFT includes a step of forming an impurity region for a source and a drain by simultaneously implanting and activating impurity ions. More particularly, the present invention includes the steps of forming a gate insulating layer and a gate ... | 02/28/2006 |
| 6972441 | Silicon germanium heterojunction bipolar transistor with step-up carbon profile A bipolar transistor having a collector connected to a base, the collector including an amount of carbon sufficient to prevent a conduction band barrier at a base-collector junction. ... | 12/06/2005 |
| 6953728 | Semiconductor device and method of manufacturing thereof This semiconductor device manufacturing method comprises the steps of: forming a thick gate oxide film (thick oxide film) in a first region of a substrate, forming a thin gate oxide film (thin oxide layer) in a second region, and then, applying oxynitridation to the... | 10/11/2005 |
| 6933545 | Hetero-bipolar transistor having the base interconnection provided on the normal mesa surface of the collector mesa The present invention provides a hetero-bipolar transistor having a new configuration of the interconnection. The bipolar transistor of the present invention includes the collector mesa, having the base and collector layers therein, includes a first side having a no... | 08/23/2005 |
| 6924201 | Heterojunction bipolar transistor and method of producing the same A heterojunction bipolar transistor of the present invention is produced from a wafer including a substrate and a collector layer of a first conductivity type, a base layer of a second conductivity type and an emitter layer of the first conductivity type sequentiall... | 08/02/2005 |
| 6917061 | AlGaAs or InGaP low turn-on voltage GaAs-based heterojunction bipolar transistor A heterojunction bipolar transistor is provided that has a reduced turn-on voltage threshold. A base spacer layer is provided and alternately an emitter layer is provided that has a lowered energy gap. The lowered energy gap of the base spacer or the emitter spacer ... | 07/12/2005 |
| 6905929 | Single poly EPROM cell having smaller size and improved data retention compatible with advanced CMOS process Leakage of a single-poly EPROM cell is prevented by eliminating field oxide isolating the source, channel, and drain from the control gate n-well, and by replacing field oxide surrounding the cell with a heavily doped surface isolation region. The EPROM cell also ut... | 06/14/2005 |
| 6894362 | Method and apparatus for a self-aligned heterojunction bipolar transistor using dielectric assisted metal liftoff process Disclosed is a manufacturing method to fabricate Heterojunction Bipolar Transistors (HBTs) that enables self-alignment of emitter and base metal contact layers with precise sub-micron spacing using a dielectric-assisted metal lift-off process. Such an HBT process re... | 05/17/2005 |
| 6873029 | Self-aligned bipolar transistor A heterojunction bipolar transistor with self-aligned features having a self-aligned dielectric sidewall spacer disposed between base contact and emitter contact, and self-aligned base mesa aligned relative to self-aligned base contact. The base contact is self-alig... | 03/29/2005 |
| 6855948 | Low base-emitter voltage heterojunction bipolar transistor A heterojunction bipolar transistor is presented, comprising a substrate having formed thereon a heterojunction bipolar transistor layer structure, and including an emitter layer. The emitter layer includes a strained, n-doped compound of indium arsenic and phosphor... | 02/15/2005 |
| 6847062 | Semiconductor device In a semiconductor device functioning as a SiGeC-HBT, an emitter/base stacked portion 20 is formed on a Si epitaxially grown layer 2. The emitter/base stacked portion 20 includes: a SiGeC spacer layer 21; a SiGeC core base layer 22 | 01/25/2005 |
| 6847063 | Semiconductor device In a semiconductor device acting as an HBT, an emitter/base laminate portion is provided on a Si epitaxially grown layer in the SiGeC-HBT. The emitter/base laminate portion includes a SiGeC spacer layer, a SiGeC core base layer containing the boron, a Si cap layer, ... | 01/25/2005 |
| 6818520 | Method for controlling critical dimension in an HBT emitter According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base. The heterojunction bipolar transistor further comprises a first nitride spacer and a second nitride spacer situated on the base, where the first nitride spacer and the secon... | 11/16/2004 |
| 6806512 | InPSb/InAs BJT device and method of making Bipolar junction transistor (BJT) devices, particularly heterojunction bipolar transistor (HBT) devices, and methods of making same are described. A combination of InPSb and ρ-type InAs is used to create extremely high speed bipolar devices which, due to reduced tu... | 10/19/2004 |
| 6797580 | Method for fabricating a bipolar transistor in a BiCMOS process and related structure According to one exemplary embodiment, a method for fabricating a bipolar transistor in a BiCMOS process comprises a step of forming an emitter window stack by sequentially depositing a base oxide layer and an antireflective coating layer on a top surface of a base,... | 09/28/2004 |
| 6784064 | Heterojunction bipolar transistor and method of making heterojunction bipolar transistor A method of making a heterojunction bipolar transistor comprises the steps of: forming a mask layer on a compound semiconductor film by using a photomask for forming an emitter; and forming the emitter by wet-etching the compound semiconductor film by using the mask... | 08/31/2004 |
| 6768139 | Transistor configuration for a bandgap circuit A transistor configuration for a bandgap circuit is configured in the form of an npn transistor. An insulated p-type well, which is surrounded by a buried n-type well, is used as a base terminal. The n-type well constitutes the emitter terminal. A negatively doped r... | 07/27/2004 |
| 6762106 | Semiconductor device and method for fabricating the same An Si/SiGe layer including an Si buffer layer, an SiGe spacer layer, a graded SiGe layer and an Si cap layer is epitaxially grown in a region corresponding to a collector opening while a polycrystalline layer is deposited on the upper surface of a nitride film, and ... | 07/13/2004 |
| 6727146 | Semiconductor device and method of manufacturing thereof This semiconductor device manufacturing method comprises the steps of: forming a thick gate oxide film (thick oxide film) in a first region of a substrate, forming a thin gate oxide film (thin oxide layer) in a second region, and then, applying oxynitridation to the... | 04/27/2004 |
| 6673687 | Method for fabrication of a heterojunction bipolar transistor According to one disclosed embodiment, a heavily doped subcollector is formed. Subsequently, a collector is fabricated over the heavily-doped subcollectoi, wherein the collector comprises a medium-doped collector layer adjacent to the subcollector and a l... | 01/06/2004 |
| 6660607 | Method for fabricating heterojunction bipolar transistors A method for fabricating a heterojunction bipolar transistor having collector, base and emitter regions is disclosed. In an exemplary embodiment of the invention, the method includes forming a silicon epitaxial layer upon a substrate, the silicon epitaxia... | 12/09/2003 |
