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| Number | Title | Issue Date |
| 8183119 | Semiconductor device fabrication method using multiple mask patterns A resist pattern (5) is formed in a dimension of a limitation of an exposure resolution over a hard mask material film (4) over a work film (3). The material film (4) is processed using the resist pattern (5) as a mask. A hard mask... | 05/22/2012 |
| 7968416 | Integrated circuit arrangement with NPN and PNP bipolar transistors and corresponding production method An integrated circuit arrangement and fabrication method is provided. The integrated circuit arrangement contains an NPN transistor and a PNP transistor. The PNP transistor contains an emitter connection region and a cutout. The cutout delimits the width of the emit... | 06/28/2011 |
| 7824996 | Semiconductor device fabrication method and semiconductor device A resist pattern (5) is formed in a dimension of a limitation of an exposure resolution over a hard mask material film (4) over a work film (3). The material film (4) is processed using the resist pattern (5) as a mask. A hard mask... | 11/02/2010 |
| 7351660 | Process for producing high performance interconnects A method for fabricating high performance vertical and horizontal electrical connections in a three dimensional semiconductor structure. A dielectric film is imprinted with a stamp pattern at high vacuum and with precise temperature and stamping pressure control. Th... | 04/01/2008 |
| 7348652 | Bulk-isolated PN diode and method of forming a bulk-isolated PN diode A technique for making a bulk isolated PN diode. Specifically, a technique is provided for making a voltage clamp with a pair of bulk isolated PN diode. Another embodiment provides for a voltage clamp with a pair of bulk isolated PN diodes in parallel with a pair of... | 03/25/2008 |
| 7300849 | Bandgap engineered mono-crystalline silicon cap layers for SiGe HBT performance enhancement A method for fabricating a heterojunction bipolar transistor (HBT) is provided. The method includes providing a substrate including a collector region; forming a compound base region over the collector region; forming a cap layer overlying the compound base region i... | 11/27/2007 |
| 7282401 | Method and apparatus for a self-aligned recessed access device (RAD) transistor gate A method used in fabrication of a recessed access device transistor gate has increased tolerance for mask misalignment. One embodiment of the invention comprises forming a vertical spacing layer over a semiconductor wafer, then etching the vertical spacing layer and... | 10/16/2007 |
| 7262471 | Drain extended PMOS transistor with increased breakdown voltage A semiconductor device (102) that includes a drain extended PMOS transistor (CT1a) is provided, as well as fabrication methods (202) therefore. In forming the PMOS transistor, a drain (124) of the transistor is formed over a region... | 08/28/2007 |
| 7253042 | Method of fabricating a high-voltage transistor with an extended drain structure A method for fabricating a high-voltage transistor with an extended drain region includes forming in a semiconductor substrate of a first conductivity type, first and second trenches that define a mesa having respective first and second sidewalls; then partially fil... | 08/07/2007 |
| 7253091 | Process for assembling three-dimensional systems on a chip and structure thus obtained A method for assembling an electronic system with a plurality of layers. Recesses in formed in one or more dielectric layers and electronic components are positioned within the recesses. One or more layers containing the components are placed on a host substrate con... | 08/07/2007 |
| 7223635 | Oriented self-location of microstructures with alignment structures An electronic apparatus comprising one or more microstructures on a substrate and a method for fabricating the electronic apparatus. The microstructures have alignment structures that allow the microstructures to be oriented in receptacles having shapes that are com... | 05/29/2007 |
| 7217609 | Semiconductor fabrication process, lateral PNP transistor, and integrated circuit A method in the fabrication of an integrated bipolar circuit comprises the steps of: providing a p-type substrate; forming in the substrate a buried n+-type region and an n-type region above the buried n+-type region; forming field isolation areas around ... | 05/15/2007 |
| 7202136 | Silicon germanium heterojunction bipolar transistor with carbon incorporation A silicon germanium heterojunction bipolar transistor device and method comprises a semiconductor region, and a diffusion region in the semiconductor region, wherein the diffusion region is boron-doped, wherein the semiconductor region comprises a carbon dopant ther... | 04/10/2007 |
| 7151035 | Semiconductor device and manufacturing method thereof A sidewall-insulation film 9 is provided on a side surface of a first opening portion 8a formed in a base extraction electrode 5B of a hetero-junction bipolar transistor, and a portion of the sidewall-insulation film 9 extends so a... | 12/19/2006 |
| 7129177 | Write head fabrication by inverting order of process steps During fabrication of a write head via holes are first opened in a gap layer, followed by formation of seed layers instead of the other way around. Moreover a first seed layer is formed, and without the first seed layer being used a second seed layer is formed. The ... | 10/31/2006 |
| 7098113 | Method and system for providing a power lateral PNP transistor using a buried power buss A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer; an emitter region between the first and second collector regions. Therefore slots are placed in each of the regions. Accor... | 08/29/2006 |
| 7037798 | Bipolar transistor structure with self-aligned raised extrinsic base and methods The invention includes methods of fabricating a bipolar transistor that adds a silicon germanium (SiGe) layer or a third insulator layer of, e.g., high pressure oxide (HIPOX), atop an emitter cap adjacent the intrinsic base prior to forming a link-up layer. This add... | 05/02/2006 |
| 7022571 | Quantum structure and forming method of the same A quantum structure and the forming method based on the difference in characteristic of two matters is provided. The forming method includes several steps. At first, providing a first dielectric layer for forming a second dielectric layer thereon. The second dielect... | 04/04/2006 |
| 7018575 | Method for assembly of complementary-shaped receptacle site and device microstructures A method for assembly including the steps of: (a) providing a plurality of microstructure components with each of the components having a bottom with the same three dimensional shape; (b) forming a mold with at least one protuberance from a surface the... | 03/28/2006 |
| 6987039 | Forming lateral bipolar junction transistor in CMOS flow A method of forming a lateral bipolar transistor without added mask in CMOS flow including a p-substrate; patterning and n-well implants; pattern and implant pocket implants for core nMOS and MOS; pattern and implants pocket implants I/O nMOS and pMOS; sidewall depo... | 01/17/2006 |
| 6974604 | Method of self-latching for adhesion during self-assembly of electronic or optical components A method for assembling components on a substrate including the steps of: (a) selectively coating at least a first receptor site of the substrate with a liquid precursor that forms a solid adhesive upon contact with an initiator; (b) providing each of the components... | 12/13/2005 |
| 6972237 | Lateral heterojunction bipolar transistor and method of manufacture using selective epitaxial growth A method for manufacturing a heterojunction bipolar transistor is provided. An intrinsic collector structure is formed on a substrate. An extrinsic base structure partially overlaps the intrinsic collector structure. An intrinsic base structure is formed adjacent th... | 12/06/2005 |
| 6908824 | Self-aligned lateral heterojunction bipolar transistor A method for manufacturing a lateral heterojunction bipolar transistor (HBT) is provided comprising a semiconductor substrate having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating... | 06/21/2005 |
| 6838346 | Method of fabricating a high-voltage transistor with a multi-layered extended drain structure A method for fabricating a high-voltage transistor with an extended drain region includes forming an epitaxial layer on a substrate, the epitaxal layer and the substrate being of a first conductivity type; then etching the epitaxial layer to form a pair of spaced-ap... | 01/04/2005 |
| 6818513 | Method of forming a field effect transistor having a lateral depletion structure A method of forming a field effect transistor device includes: forming a well region of a second conductivity type in a semiconductor substrate of a first conductivity type, the semiconductor substrate having a major surface and a drain region; forming a source regi... | 11/16/2004 |
| 6803273 | Method to salicide source-line in flash memory with STI A method of forming a semiconductor component having a conductive line (24) and a silicide region (140) that crosses a trench (72). The method involves forming nitride sidewalls (130) to protect the stack during the silicidation process. | 10/12/2004 |
| 6794237 | Lateral heterojunction bipolar transistor A heterojunction bipolar transistor (30) in a silicon-on-insulator (SOI) structure is disclosed. The transistor collector (28), heterojunction base region (20), and intrinsic emitter region (25) are formed in the thin film silicon layer (... | 09/21/2004 |
| 6790736 | Method for manufacturing and structure of semiconductor device with polysilicon definition structure In accordance with a particular embodiment of the present invention, a method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer, and an is... | 09/14/2004 |
| 6780666 | Imager photo diode capacitor structure with reduced process variation sensitivity A pixel cell having two capacitors connected in series where each capacitor has a capacitance approximating that at of the periphery capacitors and such that the effective capacitance of the series capacitors is smaller than that of each of the periphery capacitors.... | 08/24/2004 |
| 6767779 | Asymmetrical MOSFET layout for high currents and high speed operation A structure and method for a field effect transistor capable of handling high currents, comprises interleaved source and drain diffusion regions with drain diffusion contacts to a first metal level over the drain diffusions only; while a second metal level covers th... | 07/27/2004 |
| 6750105 | Method of fabricating a high-voltage transistor with a multi-layered extended drain structure A method for fabricating a high-voltage transistor with an extended drain region includes forming an epitaxial layer on a substrate, the epitaxial layer and the substrate being of a first conductivity type; then etching the epitaxial layer to form a pair of spaced-a... | 06/15/2004 |
| 6667213 | Method of fabricating a high-voltage transistor with a multi-layered extended drain structure A method for fabricating a high-voltage transistor with an extended drain region includes forming parallel arranged drift regions, each of which is interleaved with an insulating layer and a conducting layer that functions as a field plate. Source and bod... | 12/23/2003 |
| 6638807 | Technique for gated lateral bipolar transistors An improved structure and method for gated lateral bipolar transistors are provided. Embodiments of the present invention capitalize on opposing sidewalls and adjacent conductive sidewall members to conserve available surface space on the semiconductor ch... | 10/28/2003 |
| 6635544 | Method of fabricating a high-voltage transistor with a multi-layered extended drain structure A method for fabricating a high-voltage transistor with an extended drain region includes forming an epitaxial layer on a substrate, the epitaxial layer and the substrate being of a first conductivity type; then etching the epitaxial layer to form a pair ... | 10/21/2003 |
| 6583007 | Reducing secondary injection effects A method for forming a non-volatile memory (NVM) device, the method including forming two diffusion areas in a substrate, said diffusion areas forming a channel therebetween, the channel being adapted to permit movement of primary electrons to at least on... | 06/24/2003 |
| 6551869 | Lateral PNP and method of manufacture A lateral PNP is disclosed in which a substrate of a first conductivity type is used. On top of the substrate a buried region of a second conductivity type is formed. A lightly doped collector region is located above the buried region. The lateral PNP als... | 04/22/2003 |
| 6548352 | Multi-layered gate for a CMOS imager A multi-layered gate for use in a CMOS or CCD imager formed with a second gate at least partially overlapping it. The multi-layered gate is a complete gate stack having an insulating layer, a conductive layer, an optional silicide layer, and a second insu... | 04/15/2003 |
| 6541346 | Method and apparatus for a self-aligned heterojunction bipolar transistor using dielectric assisted metal liftoff process Disclosed is a manufacturing method to fabricate Heterojunction Bipolar Transistors (HBTs) that enables self-alignment of emitter and base metal contact layers with precise sub-micron spacing using a dielectric-assisted metal lift-off process. Such an HBT... | 04/01/2003 |
| 6528828 | Differential negative resistance HBT and process for fabricating the same A differential negative resistance element includes a heavily doped GaAs layer interposed between a collector layer of lightly doped GaAs and an emitter layer of heavily doped AlGaAs, is shared between a base region between the collector layer and the emi... | 03/04/2003 |
| 6501152 | Advanced lateral PNP by implant negation A lateral NPN transistor (LPNP) (102) having the lightly doped drain extension implant blocked from the emitter region (118) but not the collector region (120). Accordingly, the emitter region (118) has a more abrupt junction for high emitter injection ef... | 12/31/2002 |
