Did You Know...
...that Robert Adler has the dubious distinction of being the Father of the Couch Potato? Back in 1955 Adler was employed by what was then Zenith Radio Corp., where he was charged to invent something that would allow viewers to turn down the TV volume without leaving their chairs. After a series of flops (such as a wired contraption that people tripped over), Adler hit on the idea of using sound waves. Thus the Remote Control was born...
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| Number | Title | Issue Date |
| 7422951 | Method of fabricating self-aligned bipolar transistor The present invention provides a method of fabricating a self-aligned bipolar transistor, by which the fabricating method can be simplified by forming P+ and N+ junctions by self-alignment and by which device reliability can be enhanced. The present invention includ... | 09/09/2008 |
| 7342276 | Method and apparatus utilizing monocrystalline insulator A semiconductor device, including: a semiconductor material; a conductive element; and a substantially monocrystalline insulator disposed between the semiconductor material and the conductive eleme... | 03/11/2008 |
| 7297630 | Methods of fabricating via hole and trench A method of fabricating a via and a trench is disclosed. A disclosed method comprises: forming a via hole and a trench in a interlayer dielectric layer on a semiconductor substrate where a predetermined device is formed; depositing a thin Hf layer on the substrate; ... | 11/20/2007 |
| 7297992 | Method and structure for integration of phosphorous emitter in an NPN device in a BiCMOS process According to one exemplary embodiment, a heterojunction bipolar transistor includes a base situated on a substrate. The heterojunction bipolar transistor can be an NPN silicon-germanium heterojunction bipolar transistor, for example. The heterojunction bipolar trans... | 11/20/2007 |
| 7247924 | Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicon structures A method of modulating grain size in a polysilicon layer and devices fabricated with the method. The method comprises forming the layer of polysilicon on a substrate; and performing an ion implantation of a polysilicon grain size modulating species into the polysili... | 07/24/2007 |
| 7211482 | Method of forming a memory cell having self-aligned contact regions A memory cell of a semiconductor device and a method for forming the same, wherein the memory cell includes a substrate having active regions and field regions, a gate layer formed over the substrate, the gate layer including a plurality of access gates formed over ... | 05/01/2007 |
| 7199063 | Process for passivating polysilicon and process for fabricating polysilicon thin film transistor A process for passivating polysilicon and a process for fabricating a polysilicon thin film transistor. A polysilicon layer is formed. Next, high-pressure annealing is performed using a fluorine-containing gas, a chlorine-containing gas, an oxygen-containing gas, a ... | 04/03/2007 |
| 7169664 | Method of reducing wafer contamination by removing under-metal layers at the wafer edge According to the present invention, a metal and a barrier material, such as copper and a tantalum-based barrier material, are effectively removed from the wafer edge and especially from the bevel by using an etchant that comprises a diluted mixture of hydrofluoric a... | 01/30/2007 |
| 7169674 | Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier A diffusion barrier (and method for forming the diffusion barrier) for a field-effect transistor having a channel region and a gate electrode, includes an insulating material being disposed over the channel region. The insulating material includes nitrogen (N), and ... | 01/30/2007 |
| 7135351 | Method for controlling of thermal donor formation in high resistivity CZ silicon The present invention is directed to a single crystal Czochralski-type silicon wafer, and a process for the preparation thereof, which has at least a surface layer of high resistivity, the layer having an interstitial oxygen content which renders it incapable of for... | 11/14/2006 |
| 6958264 | Scribe lane for gettering of contaminants on SOI wafers and gettering method A method of manufacturing a semiconductor device on a silicon-on-insulator wafer including a silicon active layer having at least two die pads formed thereon, the at least two die pads separated by at least one scribe lane, including the steps of forming at least on... | 10/25/2005 |
| 6916739 | Structural element and process for its production including bonding through an amorphous hard layer A method for manufacturing structural elements provides a first part with a surface that is substantially copper and a second part with a surface of a metal. The surface of the first part is coated with a hard layer which is stable at a temperature of at least 80° ... | 07/12/2005 |
| 6897084 | Control of oxygen precipitate formation in high resistivity CZ silicon The present invention is directed to a single crystal Czochralski-type silicon wafer, and a process for the preparation thereof, which has at least a surface layer of high resistivity, the layer having an interstitial oxygen content which renders it incapable of for... | 05/24/2005 |
| 6838321 | SEMICONDUCTOR SUBSTRATE WITH DEFECTS REDUCED OR REMOVED AND METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE CAPABLE OF BIDIRECTIONALLY RETAINING BREAKDOWN VOLTAGE AND METHOD OF MANUFACTURING THE SAME An N−-type silicon substrate (1) has a bottom surface and an upper surface which are opposed to each other. In the bottom surface of the N−-type silicon substrate (1), a P-type impurity diffusion layer (3) of high conce... | 01/04/2005 |
| 6815282 | Silicon on insulator field effect transistor having shared body contact Silicon on insulator (SOI) field effect transistors (FET) with a shared body contact, a SRAM cell and array including the SOI FETs and the method of forming the SOI FETs. The SRAM cell has a hybrid SOI/bulk structure wherein the source/drain diffusions do not penetr... | 11/09/2004 |
| 6797547 | Bladed silicon-on-insulator semiconductor devices and method of making A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and side oxide layers. A polysilicon post disposed at one end of the element has a bottom portion extending thr... | 09/28/2004 |
| 6784051 | Method for fabricating semiconductor device The present invention provides a method for fabricating a semiconductor device capable of preventing a pattern at an edge area of a wafer from being lifted and acting as a particle source. The present invention includes the steps of: preparing a wafer having a first... | 08/31/2004 |
| 6777272 | Method of manufacturing an active matrix display A driver circuit integration type (monolithic type) active matrix display device having high performance is formed by using thin film transistors (TFT). While a nickel element is added t an amorphous silicon film 203, a head treatment is carried out to thereb... | 08/17/2004 |
| 6703281 | Differential laser thermal process with disposable spacers MOSFETs are fabricated with accurately defined, high and uniformly concentrated source/drain regions and extensions employing plural, sequential pre-amorphizing, implanting and laser thermal annealing steps with intervening spacer removal. Embodiments inc... | 03/09/2004 |
| 6693015 | Method for improved processing and etchback of a container capacitor A capacitor having improved size for enhanced capacitance and a method of forming the same are disclosed. In one embodiment, the capacitor is a stacked container capacitor used in a dynamic random access memory circuit. The capacitor provides a capacitor ... | 02/17/2004 |
| 6670259 | Inert atom implantation method for SOI gettering The present invention relates to a method of manufacturing a silicon-on-insulator substrate, comprising the steps of (1) providing a silicon-on-insulator semiconductor wafer having at least one surface of a silicon film; (2) implanting an inert atom into ... | 12/30/2003 |
| 6551866 | Method of manufacturing a semiconductor memory device A method of manufacturing a semiconductor memory device comprising: a step of forming a storage node in which a conductive layer 7 to be the storage node is formed in the vicinity of single crystalline silicon 3 formed on an insulator 2, a gettering step ... | 04/22/2003 |
| 6433380 | Integrated circuit capacitors having composite titanium oxide and tantalum pentoxide dielectric layers therein Methods of forming integrated circuit capacitors (e.g., DRAM capacitors) include the steps of forming a first capacitor electrode (e.g., polysilicon electrode) on a substrate and then forming a titanium nitride layer on the first capacitor electrode. A ta... | 08/13/2002 |
| 6344384 | Method of production of semiconductor device A method of production of a semiconductor device able to be miniaturized by preventing the decline of the hfe at a low current caused by an increase of a surface recombination current of a bipolar transistor and forming the external base region... | 02/05/2002 |
| 6339011 | Method of forming semiconductive active area having a proximity gettering region therein and method of processing a monocrystalline silicon substrate to have a proximity gettering region In one implementation, A method of forming semiconductive material active area having a proximity gettering region received therein includes providing a substrate comprising bulk semiconductive material. A proximity gettering region is formed within the b... | 01/15/2002 |
| 6309938 | Deuterated bipolar transistor and method of manufacture thereof A bipolar transistor and a method of manufacturing the transistor. The transistor includes: (1) a substrate having a base region, an emitter region and a base-emitter junction between said base and emitter regions and (2) a substantial concentration of an... | 10/30/2001 |
| 6165867 | Method to reduce aspect ratio of DRAM peripheral contact The present invention provides a method for reducing aspect ratio of DRAM peripheral contact so as to achieving a good contact etching and metal deposition by utilizing conventional equipment. Besides, the present invention provides a stop layer formed by... | 12/26/2000 |
| 6140172 | Conductive electrical contacts, capacitors, DRAMs, and integrated circuitry, and methods of forming conductive electrical contacts, capacitors, DRAMs and integrated circuitry The invention encompasses DRAM constructions, capacitor constructions, conductive contacts, integrated circuitry, methods of forming DRAM constructions, and methods of forming capacitor constructions. The invention includes a method of forming a contact t... | 10/31/2000 |
| 6114223 | Gettering regions and methods of forming gettering regions within a semiconductor wafer In one aspect, the invention pertains to a method of forming a gettering region within an Si semiconductor wafer, the method including: a) providing a semiconductor material wafer; b) providing a background region within the semiconductor material wafer, ... | 09/05/2000 |
| 6090645 | Fabrication method of semiconductor device with gettering treatment A fabrication method of a semiconductor device capable of effective gettering treatment even when electronic elements are further miniaturized and further integrated and a semiconductor substrate or wafer is upsized. First, a single-crystal silicon substr... | 07/18/2000 |
| 6051474 | Negative biasing of isolation trench fill to attract mobile positive ions away from bipolar device regions The tendency of mobile positive ions to be transported into device regions of a bipolar transistor is effectively minimized by surrounding the transistor with a `positive ion`-attracting electric field, preferably by applying a prescribed bias to the fill... | 04/18/2000 |
| 6048778 | Gettering regions and methods of forming gettering regions within a semiconductor wafer In one aspect, the invention pertains to a method of forming a gettering region within an Si semiconductor wafer, the method including: a) providing a semiconductor material wafer; b) providing a background region within the semiconductor material wafer, ... | 04/11/2000 |
| 6043112 | IGBT with reduced forward voltage drop and reduced switching loss The boundary between the P type silicon base and N+ buffer layer of an IGBT is intentionally damaged, as by a germanium implant, to create well defined and located damage sites for reducing lifetime in the silicon.... | 03/28/2000 |
| 5976956 | Method of controlling dopant concentrations using transient-enhanced diffusion prior to gate formation in a device Dopant atoms have coefficients of diffusion that vary due to implant damage. Damaged regions are selected and created by implanting silicon atoms into a silicon substrate prior to formation of a gate electrode. The silicon atoms act as a getter for attrac... | 11/02/1999 |
| 5895236 | Semiconductor device fabricating method having a gettering step A device isolation region and a gate oxide film are formed on a front surface of a silicon substrate, with a gate electrode formed on the gate oxide film. Next, an interlayer insulator film is formed on their entire surfaces. Then, polycrystalline silicon... | 04/20/1999 |
| 5892292 | Getterer for multi-layer wafers and method for making same A getterer structure for dielectrically isolated wafer structures such as bonded wafers. The getterer is a layer of polysilicon along the sidewalls of semiconductor regions isolated from each other by trenches. The polysilicon may be doped. The polysilico... | 04/06/1999 |
| 5773356 | Gettering regions and methods of forming gettering regions within a semiconductor wafer In one aspect, the invention pertains to a method of forming a gettering region within an Si semiconductor wafer, the method including: a) providing a semiconductor material wafer; b) providing a background region within the semiconductor material wafer, ... | 06/30/1998 |
| 5753563 | Method of removing particles by adhesive The removal of particulate contaminants, such as dust particles, from the surface of a semiconductor wafer is achieved by pressing a soft adhesive layer against the wafer surface, leaving it in place for a short time and then removing it. The adhesive is ... | 05/19/1998 |
| 5376562 | Method for forming vertical transistor structures having bipolar and MOS devices A transistor is formed as either a bipolar transistor (10) or an MOS transistor (11). Each transistor (10 or 11) has a substrate (12). Bipolar transistor (10) has a first current electrode (26) underlying a control electrode (28), and a second current ele... | 12/27/1994 |
| 5137839 | Method of manufacturing a bipolar transistor having polysilicon layer which serves as an emitter electrode and passivating dangling bonds In a bipolar transistor, a polysilicon layer formed on an emitter diffusion layer is used as an emitter electrode. After the polysilicon layer is formed, an atom is introduced into the polysilicon layer. A thermal treatment is then performed, and the atom... | 08/11/1992 |
