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"I watched his countenance closely, to see if he was not deranged ... and I was assured by other senators after he left the room that they had no confidence in it."
U.S. Senator Smith of Indiana ; After seeing Samuel Morse demonstrate the telegraph.
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| Number | Title | Issue Date |
| 8129248 | Method of producing bipolar transistor structures in a semiconductor process In the method of producing bipolar transistor structures in a semiconductor process, an advanced epitaxial trisilane process can be used without the risk of poly stringers being formed. A base window is structured in a polycrystalline silicon layer covered with an o... | 03/06/2012 |
| 8093131 | Lateral insulated gate bipolar transistor having a retrograde doping profile in base region and method of manufacture thereof In a semiconductor device of the present invention, a first base region 16 is extended to a part under a gate electrode 7 while having a vertical concentration profile of an impurity that increases from the surface of a semiconductor layer 3 and... | 01/10/2012 |
| 8067290 | Bipolar transistor with base-collector-isolation without dielectric The disclosed invention provides a method for the fabrication of a bipolar transistor having a collector region comprised within a semiconductor body separated from an overlying base region by one or more isolation cavities (e.g., air gaps) filled with low permittiv... | 11/29/2011 |
| 8021951 | Formation of longitudinal bipolar transistor with base region in trenches having emitter and collector regions disposed along portions of side surfaces of base region Provided is a semiconductor device including: a silicon substrate; at least two trenches spaced apart from each other, being in parallel with each other, and being formed by vertically etching the silicon substrate from a surface thereof; an electrically insulating ... | 09/20/2011 |
| 8003473 | Bipolar transistor with silicided sub-collector Embodiments of the invention provide a method of fabricating a semiconductor device. The method includes defining a sub-collector region in a layer of doped semiconductor material; forming an active region, a dielectric region, and a reach-through region on top of t... | 08/23/2011 |
| 7989301 | Semiconductor device with bipolar transistor and method of fabricating the same Disclosed is a semiconductor device with a bipolar transistor and method of fabricating the same. The device may include a collector region in a semiconductor substrate. A base pattern may be disposed on the collector region. A hard mask pattern may be disposed on t... | 08/02/2011 |
| 7981753 | Method and device for electrostatic discharge protection A device for providing electrostatic discharge (ESD) protection is provided. The device includes a semiconductor substrate having a drain, a source, and a gate formed therein. The drain contains a region having a resistance that is higher than the resistance of the ... | 07/19/2011 |
| 7951681 | Substrate-triggered bipolar junction transistor and ESD protection circuit An ESD protection circuit using a novel substrate-triggered lateral bipolar junction transistor (STLBJT) for providing a discharging path between power rails. The ESD protection circuit comprises an ESD detection circuit and a STLBJT device. The STLBJT device formed... | 05/31/2011 |
| 7939414 | Ion implantation and process sequence to form smaller base pick-up Methods for forming a bipolar junction transistor device are described herein. A method for forming the bipolar junction transistor device may include doping a first portion of a substrate with a first dopant to form a base pick-up region, and after doping the first... | 05/10/2011 |
| 7932155 | Structure and method for performance improvement in vertical bipolar transistors A method of forming a semiconductor device having two different strains therein is provided. The method includes forming a strain in a first region with a first straining film, and forming a second strain in a second region with a second straining film. Either of th... | 04/26/2011 |
| 7927955 | Adjustable bipolar transistors formed using a CMOS process By providing a novel bipolar device design implementation, a standard CMOS process (105-109) can be used unchanged to fabricate useful bipolar transistors (80) and other bipolar devices having adjustable properties by partially blocking the P or... | 04/19/2011 |
| 7910447 | System and method for providing a self aligned bipolar transistor using a simplified sacrificial nitride emitter A system and method are disclosed for providing a self aligned bipolar transistor using a simplified sacrificial nitride emitter. An active region of a transistor is formed and a silicon nitride sacrificial emitter is formed above the active region of the transistor... | 03/22/2011 |
| 7846805 | Self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process A structure and a process for a self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process. Embodiments include SiGe CBiCMOS with high-performance SiGe NPN transistors and PNP transistors. As the PNP transistors and NPN transistors contained diff... | 12/07/2010 |
| 7816221 | Dielectric ledge for high frequency devices High frequency performance of (e.g., silicon) bipolar devices (40, 100, 100″) is improved by reducing the capacitive coupling (Cbc) between the extrinsic base contact (46) and the collector (44, 44′, 44″). A dielectric ledge (453, 453... | 10/19/2010 |
| 7811894 | Bipolar junction transistor and manufacturing method thereof An improved bipolar junction transistor and a method for manufacturing the same are provided. The bipolar junction transistor includes: a buried layer and a high concentration N-type collector region in a P-type semiconductor substrate; a low concentration P-type ba... | 10/12/2010 |
| 7807539 | Ion implantation and process sequence to form smaller base pick-up Methods for forming a bipolar junction transistor device are described herein. A method for forming the bipolar junction transistor device may include doping a first portion of a substrate with a first dopant to form a base pick-up region, and after doping the first... | 10/05/2010 |
| 7795102 | ESD high frequency diodes In a SiGe BJT process, a diode is formed by defining a p-n junction between the BJT collector and BJT internal base, blocking the external gate regions of the BJT and doping the emitter poly of the BJT with the same dopant type as the internal base thereby using the... | 09/14/2010 |
| 7785974 | Methods of employing a thin oxide mask for high dose implants A method for forming a bipolar transistor device includes providing a semiconductor substrate. An oxide layer is formed on the semiconductor substrate. The oxide layer is patterned to form an opening that exposes a portion of the semiconductor substrate. A dopant, s... | 08/31/2010 |
| 7691716 | Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation The present invention provides a “subcollector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped subcollector. Instead, the inventive vertical SOI BJT uses a back gate-induced, majority carrier accumulation layer as th... | 04/06/2010 |
| 7674681 | Semiconductor device and method for manufacturing the same Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes a semiconductor substrate including first and second well areas doped with second conductive ions, a third well area in the first well and doped with the ... | 03/09/2010 |
| 7666749 | SiGe semiconductor device and method of manufacturing the same Provided are a SiGe semiconductor device and a method of manufacturing the same. The method includes the steps of: forming a buried collector by doping impurity ions into a buried collector region formed on a substrate; forming a collector layer which is an active r... | 02/23/2010 |
| 7638404 | Method for forming low temperature polysilicon thin film transistor with low doped drain structure A method for forming a low temperature polysilicon thin film transistor with a low doped drain structure comprises: a) forming a polysilicon island on a substrate; b) forming a dielectric layer, a metal layer and a cap layer in sequence cover to the polysilicon isla... | 12/29/2009 |
| 7622357 | Semiconductor device structures with backside contacts for improved heat dissipation and reduced parasitic resistance The present invention relates to a device structure that comprises a substrate with front and back surfaces, and at least one semiconductor device with a first conductive structure located in the substrate and a second conductive structure located thereover. A first... | 11/24/2009 |
| 7618871 | Method for the production of a bipolar transistor comprising an improved base terminal For the production of an improved bipolar transistor comprising a low-resistance base terminal, a dielectric layer is deposited over the semiconductor substrate and is highly doped via an implantation mask. In a subsequent controlled thermal step, the dopant is then... | 11/17/2009 |
| 7615455 | Integrated circuit bipolar transistor A bipolar transistor having a base region resting by its lower surface on a collector region and surrounded with a first insulating layer, a base contact conductive region in contact with an external upper peripheral region of the base region, a second insulating re... | 11/10/2009 |
| 7611953 | Bipolar transistor with isolation and direct contacts A bipolar transistor has a collector that is contacted directly beneath a base-collector junction by metallization to reduce collector resistance. A conventional reach-through and buried layer, as well as their associated resistance, are eliminated. The transistor i... | 11/03/2009 |
| 7605046 | Active matrix structure for a display device and method for its manufacture The invention relates to an active matrix structure and method for manufacturing the active matrix structure for a display device, wherein the structure includes: providing a matrix substrate with a number of row lines and a number of column lines, with each point o... | 10/20/2009 |
| 7595249 | Bipolar transistors with vertical structures A method for fabricating a bipolar transistor includes forming a vertical sequence of semiconductor layers, forming an implant mask on the last formed semiconductor layer, and implanting dopant ions into a portion of one or more of the semiconductor layers. The sequ... | 09/29/2009 |
| 7541248 | Integrated semiconductor device and method of manufacturing thereof An integrated semiconductor device containing semiconductor elements that have respective desired on-resistances and breakdown voltages achieves appropriate characteristics as a whole of the integrated semiconductor element. The integrated semiconductor device inclu... | 06/02/2009 |
| 7521327 | High f and fbipolar transistor and method of making same A high fT and fmax bipolar transistor includes an emitter, a base, and a collector. The emitter has a lower portion and an upper portion that extends beyond the lower portion. The base includes an intrinsic base and an extrinsic base. The intri... | 04/21/2009 |
| 7517768 | Method for fabricating a heterojunction bipolar transistor A bipolar transistor with a SiGe:C film and a seed layer forming beneath the SiGe:C film and methods of making same. The method includes placing a substrate in a reactor chamber and introducing a silicon source gas into the reactor chamber to form a silicon seed lay... | 04/14/2009 |
| 7494887 | Method and apparatus for fabricating heterojunction bipolar transistors with simultaneous low base resistance and short base transit time A method for fabricating heterojunction bipolar transistors that exhibit simultaneous low base resistance and short base transit times, which translate into semiconductor devices with low power consumption and fast switching times, is presented. The method comprises... | 02/24/2009 |
| 7488662 | Self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process A structure and a process for a self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process. Embodiments include SiGe CBiCMOS with high-performance SiGe NPN transistors and PNP transistors. As the PNP transistors and NPN transistors contained diff... | 02/10/2009 |
| 7485537 | Method of fabricating a vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness The present invention provides a a method of fabricating bipolar junction transistors (BJTs) on selected areas of a very thin buried oxide (BOX) using a conventional silicon-on-insulator (SOI) starting wafer with a thick BOX. The reduced BOX thickness underneath the... | 02/03/2009 |
| 7473610 | Local collector implant structure for heterojunction bipolar transistors and method of forming the same A method of forming a heterojunction bipolar transistor (HBT) device is disclosed. The method includes forming an intrinsic base layer over a collector layer; forming a sacrificial block structure over the intrinsic base layer; formina a sacrificial spacer layer sur... | 01/06/2009 |
| 7473609 | Surface treatment in preparation for contact placement A contact is formed on indium-phosphide material. Regions of the indium-phosphide material are exposed. An energetic bombardment is performed on exposed regions of the indium-phosphide material. Metal is deposited on the exposed regions of the indium-phosphide mater... | 01/06/2009 |
| 7470594 | System and method for controlling the formation of an interfacial oxide layer in a polysilicon emitter transistor A method is disclosed for controlling the formation of an interfacial oxide layer in a polysilicon emitter transistor device. The interfacial oxide layer is formed between an underlying substrate of single crystal silicon and an upper layer of polysilicon. The curre... | 12/30/2008 |
| 7462546 | Collector tailored structures for integration of binary junction transistors A bipolar transistor is formed in an integrated BiCMOS process. A buried layer is formed in a semiconductor body. An intrinsic dilute mask is formed over the buried layer that covers at least a portion of a selected region of a target deep well region. The intrinsic... | 12/09/2008 |
| 7459367 | Method of forming a vertical P-N junction device A P-N junction device and method of forming the same are disclosed. The P-N junction device may include a P-N diode, a PiN diode or a thyristor. The P-N junction device may have a monocrystalline or polycrystalline raised anode. In one embodiment, the P-N junction d... | 12/02/2008 |
| 7459368 | Method for manufacturing integrated circuits having silicon-germanium heterobipolar transistors Method for manufacturing integrated circuits having silicon-germanium heterobipolar transistors, wherein a collector semiconductor region is created, an etch stop layer is created on a connection region, an opening is introduced into this etch stop layer, semiconduc... | 12/02/2008 |
