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An armor with rollers is provided that enables a user to move in all positions by rolling on a hard and smooth surface while constantly varying his bearing points on the ground.
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| Number | Title | Issue Date |
| 8101489 | Approach to reduce the contact resistance A method for fabricating a semiconductor device is disclosed. First, a semiconductor substrate having a doped region(s) is provided. Thereafter, a pre-amorphous implantation process and neutral (or non-neutral) species implantation process is performed over the dope... | 01/24/2012 |
| 7998823 | Method for reducing leakage currents caused by misalignment of a contact structure by increasing an error tolerance of the contact patterning process By forming an additional doped region with increased junction depth at areas in which contact regions may connect to drain and source regions, any contact irregularities may be embedded into the additional doped region, thereby reducing the risk for leakage currents... | 08/16/2011 |
| 7888224 | Method for forming a shallow junction region using defect engineering and laser annealing A method for forming a shallow junction region in a crystalline semiconductor substrate and method for fabricating a semiconductor device having the shallow junction region includes a defect engineering step in which first ions are introduced into a first region of ... | 02/15/2011 |
| 7767536 | Semiconductor device and fabricating method thereof A semiconductor device and fabrication method thereof are disclosed. An example semiconductor device includes a semiconductor substrate having a device isolation area defining an active area; a gate oxide layer formed on the active area of the substrate; a gate on t... | 08/03/2010 |
| 7759210 | Method for forming a MOS device with reduced transient enhanced diffusion A method for forming a MOS device on a semiconductor substrate includes steps of: forming a gate structure on the semiconductor substrate; implanting ions into the semiconductor substrate for forming one or more lightly doped drain structures adjacent to the gate st... | 07/20/2010 |
| 7547606 | Semiconductor device and method of manufacturing the same An exemplary method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a gate insulation layer on a semiconductor substrate; forming a plurality of gate electrodes on the gate insulation layer; forming pocket... | 06/16/2009 |
| 7439563 | High-breakdown-voltage semiconductor device A high-breakdown-voltage semiconductor device comprises a high-resistance semiconductor layer, trenches formed on the surface thereof in a longitudinal plane shape and in parallel, first regions formed on the semiconductor layer to be sandwiched between adjacent one... | 10/21/2008 |
| 7402451 | Optimized transistor for imager device An imager device that has mitigated dark current leakage and punch-through protection. The transistor associated with the photoconversion device is formed with a single (i.e, one-sided) active area extension region on one side of the transistor gate opposite the pho... | 07/22/2008 |
| 7399669 | Semiconductor devices and methods for fabricating the same including forming an amorphous region in an interface between a device isolation layer and a source/drain diffusion layer Semiconductor devices and methods for fabricating the same are disclosed in which an amorphous layer is formed in an interface between a device isolation layer and a source or drain region to stably thin a silicide layer formed in the interface. A leakage current of... | 07/15/2008 |
| 7358168 | Ion implantation method for forming a shallow junction A shallow junction that previously would require the use of a low-energy ion implanter can be directly formed by high-energy or middle-energy ion implanters such that the manufacturer need not purchase a new low-energy ion implanter. In one embodiment, an ion-implan... | 04/15/2008 |
| 7358567 | High-voltage MOS device and fabrication thereof A HV-MOS device is described, including a substrate, a gate dielectric layer and a gate, a channel region, two doped regions as a source and a drain, a field isolation layer between the gate and at least one of the two doped regions, a drift region and a modifying d... | 04/15/2008 |
| 7355215 | Field effect transistors (FETs) having multi-watt output power at millimeter-wave frequencies High electron mobility transistors (HEMT) are provided having an output power of greater than 3.0 Watts when operated at a frequency of at least 30 GHz. The HEMT has a power added efficiency (PAE) of at least about 20 percent and/or a gain of at least about 7.5 dB. ... | 04/08/2008 |
| 7354838 | Technique for forming a contact insulation layer with enhanced stress transfer efficiency By removing an outer spacer, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, a high degree of process compatibility with conventional processes is obtained, while at the same time a contact liner layer may ... | 04/08/2008 |
| 7338855 | Method for fabricating semiconductor device A method for fabricating a semiconductor device is provided, wherein a large MIM capacitor including an uneven surface if formed to increase capacitance. The method includes forming a polysilicon layer on a lower metal layer by plasma-enhanced chemical vapor deposit... | 03/04/2008 |
| RE40138 | Method for improving hot carrier lifetime via a nitrogen implantation procedure performed before or after a Teos liner deposition A process for fabricating input/output, N channel, (I/O NMOS) devices, featuring an ion implanted nitrogen region, used to reduce hot carrier electron, (HEC), injection, has been developed. The process features implanting a nitorgen region, at the interface of an ov... | 03/04/2008 |
| 7329583 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 02/12/2008 |
| 7314787 | Method of manufacturing a semiconductor device A manufacturing method of a semiconductor device disclosed herein comprises: forming a convex first protrusion; forming a first film, of which a surface is higher than the first protrusion; forming a mask portion on the first film; and etching the first film with th... | 01/01/2008 |
| 7301221 | Controlling diffusion in doped semiconductor regions A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of impurity elements, including at least one dopant element. Selection of a plurality of impurity elements inc... | 11/27/2007 |
| 7294551 | Semiconductor device and method for manufacturing the same A semiconductor device has a gate electrode formed on a P type semiconductor substrate via gate oxide films. A first low concentration (LN type) drain region is made adjacent to one end of the gate electrode. A second low concentration (SLN type) drain region is for... | 11/13/2007 |
| 7276431 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/02/2007 |
| 7268052 | Method for reducing soft error rates of memory cells In one embodiment, a method of fabricating a transistor for a memory cell includes the steps of performing a counter doping implant before or after a source/drain implant. The counter doping implant may comprise one or more implant steps that move a metallurgical ju... | 09/11/2007 |
| 7232729 | Method for manufacturing a double bitline implant The present invention provides a method of fabricating a doped semiconductor region comprising selectively implanting a first impurity to form a shallow heavily doped region. The method further comprises selectively implanting the first impurity to also form a deep ... | 06/19/2007 |
| 7221021 | Method of forming high voltage devices with retrograde well A high voltage device with retrograde well is disclosed. The device comprises a substrate, a gate region formed on the substrate, and a retrograde well placed in the substrate next to the gate region, wherein the retrograde well reduces a dopant concentration on the... | 05/22/2007 |
| 7220646 | Integrated circuit structure with improved LDMOS design A semiconductor integrated circuit including an LDMOS device structure comprises a semiconductor layer with a pair of spaced-apart field effect gate structures over an upper surface of the semiconductor layer. First and second spaced-apart source regions of a first ... | 05/22/2007 |
| 7214986 | Semiconductor device, manufacturing method thereof, and display device A multi-gate structure is used and a width (d1) of a high concentration impurity region sandwiched by two channel forming regions in a channel length direction is set to be shorter than a width (d2) of low concentration impurity regions in the channel ... | 05/08/2007 |
| 7214591 | Method of fabricating high-voltage MOS device A HV-MOS device is described, including a substrate, a gate dielectric layer and a gate, a channel region, two doped regions as a source and a drain, a field isolation layer between the gate and at least one of the two doped regions, a drift region and a modifying d... | 05/08/2007 |
| 7211482 | Method of forming a memory cell having self-aligned contact regions A memory cell of a semiconductor device and a method for forming the same, wherein the memory cell includes a substrate having active regions and field regions, a gate layer formed over the substrate, the gate layer including a plurality of access gates formed over ... | 05/01/2007 |
| 7208385 | LDMOS transistor with enhanced termination region for high breakdown voltage with on-resistance A structure for making a LDMOS transistor (100) includes an interdigitated source finger (26) and a drain finger (21) on a substrate (15). Termination regions (35, 37) are formed at the tips of the source finger and drain finger. A... | 04/24/2007 |
| 7202134 | Method of forming transistors with ultra-short gate feature A gate electrode is formed over but insulated from a semiconductor body region for each of first and second transistors. A DDD implant is carried out to from DDD source and DDD drain regions in the body region for the first transistor. After the DDD implant, off-set... | 04/10/2007 |
| 7192853 | Method of improving the breakdown voltage of a diffused semiconductor junction A method is provided for forming a graded junction in a semiconductor material having a first conductivity type. Dopant having a second conductivity type opposite the first conductivity type is introduced into a selected region of the semiconductor material to defin... | 03/20/2007 |
| 7190028 | Semiconductor-on-insulator constructions The invention includes semiconductor constructions having a thin film stacked resistor in electrical connection with a source/drain region of a transistor device. The resistor includes first and second crystalline layers which may or may not differ from one another.... | 03/13/2007 |
| 7189623 | Semiconductor processing method and field effect transistor A method of forming a transistor gate includes forming a gate oxide layer over a semiconductive substrate. Chlorine is provided within the gate oxide layer. A gate is formed proximate the gate oxide layer. In another method, a gate and a gate oxide layer are formed ... | 03/13/2007 |
| 7183573 | Disposable spacer for symmetric and asymmetric Schottky contact to SOI mosfet A silicon on insulator transistor is disclosed which has a Schottky contact to the body. The Schottky contact may be formed on the source and/or drain side of the gate conductor. A spacer, with at least a part thereof being disposable, is formed on the sidewalls of ... | 02/27/2007 |
| 7176091 | Drain-extended MOS transistors and methods for making the same Drain-extended MOS transistors (T1, T2) and semiconductor devices (102) are described, as well as fabrication methods (202) therefor, in which a p-buried layer (130) is formed prior to formation of epitaxial silicon (106) ov... | 02/13/2007 |
| 7172933 | Recessed polysilicon gate structure for a strained silicon MOSFET device A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate... | 02/06/2007 |
| 7166517 | Semiconductor device and method of manufacture thereof The present invention provides a method of manufacturing a semiconductor device which includes an amorphous semiconductor film forming treatment of supplying a starting material gas containing germanium to a semiconductor substrate, thereby forming an amorphous semi... | 01/23/2007 |
| 7148145 | Semiconductor device having T-shaped gate structure comprising in situ sidewall spacers and method of forming the semiconductor device Polysilicon lines are formed, featuring an upper portion extending beyond the lower portion that defines the required CD. Accordingly, metal silicide layers of increased dimensions can be formed on the upper portion of the polysilicon lines so that the resulting gat... | 12/12/2006 |
| 7141477 | Semiconductor device and method for fabricating the same Into a channel formation region of a semiconductor substrate of p-type silicon, indium ions are implanted at an implantation energy of about 70 keV and a dose of about 5×1013/cm2, thereby forming a p-doped channel layer. Next, germanium ions a... | 11/28/2006 |
| 7141455 | Method to manufacture LDMOS transistors with improved threshold voltage control A double diffused region (65), (75), (85) is formed in an epitaxial layer (20). The double diffused region is formed by first implanting light implant specie such as boron through an opening in a photoresist layer prior to a hard bake pro... | 11/28/2006 |
| 7138688 | Doping method and semiconductor device fabricated using the method A doping method includes the step of attaching molecules or clusters to the surface of a semiconductor substrate to enable charge transfer from the molecules or clusters to the substrate surface, thereby inducing carriers underneath the substrate surface. A semicond... | 11/21/2006 |
