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| Number | Title | Issue Date |
| 7682917 | Disposable metallic or semiconductor gate spacer A disposable spacer is formed directly on or in close proximity to the sidewalls of a gate electrode and a gate dielectric. The disposable spacer comprises a material that scavenges oxygen such as a metal, a metal nitride, or a semiconductor material having high rea... | 03/23/2010 |
| 7432168 | Method for fabricating semiconductor device with thin gate spacer A method for fabricating a transistor. A substrate having a gate electrode thereon and insulated therefrom is provided. A first gate spacer with a first dielectric material is formed on the sidewalls of the gate electrode. A liner with a second dielectric material i... | 10/07/2008 |
| 7429527 | Method of manufacturing self-aligned contact openings A method of manufacturing self-aligned contact openings is provided. A substrate having a number of device structures is provided and the top of the device structures is higher than the surface of the substrate. A first dielectric layer and a conductive layer are se... | 09/30/2008 |
| 7419870 | Method of manufacturing a flash memory device Provided is a method of manufacturing a flash memory device. In the method, after forming a cell string and source/drain selection transistors, it forms a first oxide film in which a sidewall oxide film and a buffering oxide film are stacked, a nitride film, and a s... | 09/02/2008 |
| 7419879 | Transistor having gate dielectric layer of partial thickness difference and method of fabricating the same A transistor having a gate dielectric layer of partial thickness difference and a method of fabricating the same are provided. The method includes forming a gate dielectric layer having a main portion with a relatively thin thickness formed on a semiconductor substr... | 09/02/2008 |
| 7371631 | Method of manufacturing a nonvolatile semiconductor memory device, and a nonvolatile semiconductor memory device For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-... | 05/13/2008 |
| 7368373 | Method for manufacturing semiconductor devices and plug A method for manufacturing a semiconductor device is disclosed suitable for a substrate having a first conducting structure and a first dielectric layer, wherein the dielectric layer covers the first conductive structure. The method includes the steps of forming a s... | 05/06/2008 |
| 7364995 | Method of forming reduced short channel field effect transistor A method for manufacturing a semiconductor device capable of reducing a short channel effect, whereby the semiconductor device includes a pair of impurity regions for a source and a drain formed on a semiconductor substrate, a gate having a gate electrode used to co... | 04/29/2008 |
| 7361564 | Method of manufacturing high-voltage device A method of manufacturing a high-voltage device DDD (Double Doped Drain) ion implantation process is performed at a tilt angle in order to form a smooth junction profile. Accordingly, the intensity of an electric field can be reduced and breakdown voltage margin can... | 04/22/2008 |
| 7355245 | Structure for reducing overlap capacitance in field effect transistors A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extend... | 04/08/2008 |
| 7354838 | Technique for forming a contact insulation layer with enhanced stress transfer efficiency By removing an outer spacer, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, a high degree of process compatibility with conventional processes is obtained, while at the same time a contact liner layer may ... | 04/08/2008 |
| 7351629 | Method of forming non-volatile memory device A non-volatile memory device comprises an active region disposed in a predetermined region of a semiconductor substrate, a selection gate electrode crossing over the active region, and a floating gate electrode disposed on the active region parallel to the selection... | 04/01/2008 |
| 7338870 | Methods of fabricating semiconductor devices Methods of recovering damage on a semiconductor device by performing a hydrogen annealing process are disclosed. An example disclosed method includes forming an STI structure on a semiconductor substrate; forming a gate electrode and spacers on the sidewalls of the ... | 03/04/2008 |
| 7335567 | Gate electrodes of semiconductor devices and methods of manufacturing the same Gate electrodes of semiconductor devices and methods of manufacturing the same are disclosed. An example method comprises: sequentially forming a gate oxide layer and a sacrificial buffer layer on a semiconductor substrate; patterning the sacrificial buffer layer to... | 02/26/2008 |
| 7323388 | SONOS memory cells and arrays and method of forming the same A trench (2) is fabricated in a silicon body (1). The walls (4) of the trench are provided with a nitrogen implantation (6). An oxide layer between the source/drain regions (5) and a word line applied on the top side grows to a gre... | 01/29/2008 |
| 7319259 | Structure and method for accurate deep trench resistance measurement A test structure for implementing resistance measurement of a deep trench formed in a semiconductor device includes a pair of deep trenches formed within a semiconductor substrate. The pair of deep trenches has a dielectric material formed on side and bottom surface... | 01/15/2008 |
| 7312129 | Method for producing two gates controlling the same channel A semiconductor process and apparatus use a predetermined sequence of patterning and etching steps to etch a gate stack (62) formed over a substrate (11) and a first spacer structure (42), thereby forming etched gate structures (72, 74) t... | 12/25/2007 |
| 7279734 | MOS transistor The present invention relates to a MOS transistor which is capable of compensating the shortcomings of the conventional MOS transistor having three gate electrodes. In order to achieve the object the MOS transistor of the present invention is characterized in that t... | 10/09/2007 |
| 7268042 | Nonvolatile semiconductor memory and making method thereof A nonvolatile semiconductor memory device of a split gate structure having a gate of low resistance suitable to the arrangement of a memory cell array is provided. When being formed of a side wall spacer, a memory gate is formed of polycrystal silicon and then repla... | 09/11/2007 |
| 7265425 | Semiconductor device employing an extension spacer and a method of forming the same A semiconductor device formed on a semiconductor substrate and a method of forming the same. In one embodiment, the semiconductor device includes a gate over the semiconductor substrate and a dielectric liner on a sidewall of the gate. The semiconductor device also ... | 09/04/2007 |
| 7262456 | Bit line structure and production method thereof The disclosure relates to a bit line structure and an associated production method for the bit line structure. In the bit line structure, at least in a region of a second contact and a plurality of first contact adjoining the latter, an isolation trench is filled wi... | 08/28/2007 |
| 7259062 | Method of making a magnetic tunnel junction device A method of making a magnetic tunnel junction device is disclosed. The magnetic tunnel junction device includes a magnetic tunnel junction stack and an electrically non-conductive spacer in contact with a portion of the magnetic tunnel junction stack. The spacer ele... | 08/21/2007 |
| 7253033 | Method of manufacturing a semiconductor device that includes implanting in multiple directions a high concentration region In a complete depletion type SOI transistor, the roll-off of a threshold value is suppressed, independently from the formation of an SOI film to be thinner. As for a semiconductor device (1), the impurity concentration in a channel formation portion (10 | 08/07/2007 |
| 7244994 | Laterally diffused metal oxide semiconductor device and method of forming the same A transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the laterally diffused metal oxide ... | 07/17/2007 |
| 7242063 | Symmetric non-intrusive and covert technique to render a transistor permanently non-operable A technique for and structures for camouflaging an integrated circuit structure. The technique including forming active areas of a first conductivity type and LDD regions of a second conductivity type resulting in a transistor that is always non-operational when sta... | 07/10/2007 |
| 7232729 | Method for manufacturing a double bitline implant The present invention provides a method of fabricating a doped semiconductor region comprising selectively implanting a first impurity to form a shallow heavily doped region. The method further comprises selectively implanting the first impurity to also form a deep ... | 06/19/2007 |
| 7230302 | Laterally diffused metal oxide semiconductor device and method of forming the same A transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the laterally diffused metal oxide ... | 06/12/2007 |
| 7227230 | Low-K gate spacers by fluorine implantation A MOSFET device and a method of fabricating a MOSFET device having low-K dielectric oxide gate sidewall spacers produced by fluorine implantation. The present invention implants fluorine into the gate oxide sidewall spacers which is used to alter the properties of a... | 06/05/2007 |
| 7220649 | Method of manufacturing semiconductor device and the semiconductor device manufactured by the method The method of manufacturing the semiconductor device that includes a high voltage MOS transistor with high operating voltage under both high and low gate voltages with low-cost is disclosed. When manufacturing the high voltage MOS transistor, a portion of a gate ins... | 05/22/2007 |
| 7217977 | Covert transformation of transistor properties as a circuit protection method A technique for and structures for camouflaging an integrated circuit structure. The technique includes the use of a light density dopant (LDD) region of opposite type from the active regions resulting in a transistor that is always off when standard voltages are ap... | 05/15/2007 |
| 7217624 | Non-volatile memory device with conductive sidewall spacer and method for fabricating the same The present invention relates to a non-volatile memory device having conductive sidewall spacers and a method for fabricating the same. The non-volatile memory device includes: a substrate; a gate insulation layer formed on the substrate; a gate structure formed on ... | 05/15/2007 |
| 7211872 | Device having recessed spacers for improved salicide resistance on polysilicon gates A method and device for improved salicide resistance in polysilicon gates under 0.20 μm. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electr... | 05/01/2007 |
| 7192827 | Methods of forming capacitor structures The invention includes a method of forming a capacitor structure. A first electrical node is formed, and a layer of metallic aluminum is formed over the first electrical node. Subsequently, an entirety of the metallic aluminum within the layer is transformed into on... | 03/20/2007 |
| 7189623 | Semiconductor processing method and field effect transistor A method of forming a transistor gate includes forming a gate oxide layer over a semiconductive substrate. Chlorine is provided within the gate oxide layer. A gate is formed proximate the gate oxide layer. In another method, a gate and a gate oxide layer are formed ... | 03/13/2007 |
| 7186632 | Method of fabricating a semiconductor device having a decreased concentration of phosphorus impurities in polysilicon In a method for manufacturing a semiconductor device having a laminated gate electrode, a phosphorus-doped polysilicon is formed on a gate oxide film. A high-melting metal or a compound of a high-melting metal and silicon is formed on the polysilicon. Phosphorus is ... | 03/06/2007 |
| 7187031 | Semiconductor device having a low dielectric constant film and manufacturing method thereof A semiconductor device has a structure that reduces the parasitic capacitance by using a film with a low relative dielectric constant as the side wall material of the gate. The material with a low relative dielectric constant is preferably a material whose relative ... | 03/06/2007 |
| 7172944 | Method of fabricating a semiconductor device having an elevated source/drain The present invention provides a semiconductor device having an elevated source/drain and a method of fabricating the same. In the semiconductor device, an active region is defined at a predetermined region of a semiconductor substrate and a gate electrode is formed... | 02/06/2007 |
| 7169674 | Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier A diffusion barrier (and method for forming the diffusion barrier) for a field-effect transistor having a channel region and a gate electrode, includes an insulating material being disposed over the channel region. The insulating material includes nitrogen (N), and ... | 01/30/2007 |
| 7170137 | Semiconductor device and method of manufacturing the same A semiconductor device includes a semiconductor substrate having a first conductivity type. A pair of source/drain areas having a second conductivity type is formed on a surface of the semiconductor substrate. A gate insulating film is provided on a channel area bet... | 01/30/2007 |
| 7169678 | Method of forming a semiconductor device using a silicide etching mask Semiconductor devices and methods for fabricating a silicide of a semiconductor device are disclosed. An illustrated method comprises: forming a gate electrode; depositing an insulating layer; removing a predetermined portion of the insulating layer in order to expo... | 01/30/2007 |
