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| Number | Title | Issue Date |
| 8143132 | Transistor including a high-K metal gate electrode structure formed on the basis of a simplified spacer regime In sophisticated semiconductor devices, the threshold voltage adjustment of high-k metal gate electrode structures may be accomplished by a work function metal species provided in an early manufacturing stage. For this purpose, a protective sidewall spacer structure... | 03/27/2012 |
| 8143131 | Method of fabricating spacers in a strained semiconductor device The present disclosure provides a method for fabricating a semiconductor device that includes forming a gate stack over a silicon substrate, forming dummy spacers on sidewalls of the gate stack, isotropically etching the silicon substrate to form recess regions on e... | 03/27/2012 |
| 8124488 | Method of fabricating memory A method of fabricating a memory is provided. A substrate comprising a memory region and a periphery region is provided. A plurality of gates is formed on the substrate and a first spacer is formed on a sidewall of each gate, where a plurality of openings is formed ... | 02/28/2012 |
| 8110470 | Asymmetrical transistor device and method of fabrication Embodiments of the invention provide an asymmetrical transistor device comprising a semiconductor substrate, a source region, a drain region and a channel region. The channel region is provided between the source and drain regions, the source, drain and channel regi... | 02/07/2012 |
| 8053323 | Patterning methodology for uniformity control The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patternable layer over a substrate. The method includes forming a first layer over the patternable layer. The method includes forming a second layer over th... | 11/08/2011 |
| 8043921 | Nitride removal while protecting semiconductor surfaces for forming shallow junctions A method of removing silicon nitride over a semiconductor surface for forming shallow junctions. Sidewall spacers are formed along sidewalls of a gate stack that together define lightly doped drain (LDD) regions or source/drain (S/D) regions. At least one of the sid... | 10/25/2011 |
| 7998822 | Semiconductor fabrication process including silicide stringer removal processing A semiconductor fabrication process includes forming a gate electrode (112) overlying a gate dielectric (114) overlying a semiconductor substrate (104) of a wafer (101) and a liner dielectric layer (116) including vertical portions... | 08/16/2011 |
| 7994015 | NMOS transistor devices and methods for fabricating same NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, a method for forming an NMOS transistor may include providing a substrate having a p-type silicon region and a... | 08/09/2011 |
| 7989300 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device includes forming a gate insulating film over a semiconductor substrate, forming a silicon film over the gate insulating film, forming a resist pattern over the silicon film, etching the silicon film to form a protrusi... | 08/02/2011 |
| 7947560 | Method of nickel disilicide formation and method of nickel disilicate source/drain formation A method for forming silicide includes the steps of: forming a nickel film on a silicon layer (or a silicon substrate); introducing nitrogen into at least one of the nickel film and the interface between the nickel film and the silicon layer (or the silicon substrat... | 05/24/2011 |
| 7923337 | Fin field effect transistor devices with self-aligned source and drain regions Improved fin field effect transistor (FinFET) devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a field effect transistor device comprises the following steps. A substrate is provided having a silicon layer thereon... | 04/12/2011 |
| 7919380 | Method of manufacturing a transistor in semiconductor device having a gate electrode located between the trenches formed in low-concentration regions of the source and drain regions including high-concentration regions formed at the bottom of the trenches The present invention relates to a transistor in a semiconductor device and method of manufacturing the same. Trenches are formed in a semiconductor substrate at gate edges. Low-concentration impurity regions are then formed at the sidewalls and the bottoms of the t... | 04/05/2011 |
| 7906400 | Method of manufacturing a semiconductor device having transistors and semiconductor device having transistors A method of manufacturing a semiconductor device includes forming a first mask pattern exposing a first region for forming a first transistor and a second region for forming a second transistor, performing a first ion implantation for forming well regions using the ... | 03/15/2011 |
| 7902032 | Method for forming strained channel PMOS devices and integrated circuits therefrom An integrated circuit (IC) includes a plurality of compressively strained PMOS transistors. The IC includes a substrate having a semiconductor surface. A gate stack is formed in or on the semiconductor surface and includes a gate electrode on a gate dielectric, wher... | 03/08/2011 |
| 7883981 | Method for manufacturing flash memory device Embodiments relate to a flash memory device and a method for manufacturing a flash memory device. According to embodiments, a method may include forming a gate on and/or over a semiconductor substrate on and/or over which a device isolation film may be formed, formi... | 02/08/2011 |
| 7838373 | Replacement spacers for MOSFET fringe capacitance reduction and processes of making same A process includes planarizing a microelectronic device that includes a gate stack and adjacent trench contacts. The process also includes removing a gate spacer at the gate stack and replacing the gate spacer with a dielectric that results in a lowered overlap capa... | 11/23/2010 |
| 7820518 | Transistor fabrication methods and structures thereof Methods of fabricating transistors and semiconductor devices and structures thereof are disclosed. In one embodiment, a method of fabricating a transistor includes forming a gate dielectric over a workpiece, forming a gate over the gate dielectric, and forming a str... | 10/26/2010 |
| 7799650 | Method for making a transistor with a stressor A method for forming a semiconductor device on a semiconductor material layer includes forming a gate structure over the semiconductor material layer. The method further includes forming a first nitride spacer adjacent to the gate structure and forming source/drain ... | 09/21/2010 |
| 7772076 | Method of manufacturing semiconductor device using dummy gate wiring layer A method of manufacturing a semiconductor device includes forming a dummy gate wiring layer having a side surface and an upper surface on a first area of one major surface of a substrate, the major surface of the substrate including the first area and a second area,... | 08/10/2010 |
| 7759208 | Low temperature ion implantation for improved silicide contacts Embodiments of the present invention provide a method that cools a substrate to a temperature below 10° C. and then implants ions into the substrate while the temperature of the substrate is below 10° C. The implanting causes damage to a first depth of the substra... | 07/20/2010 |
| 7759207 | Integrated circuit system employing stress memorization transfer An integrated circuit system that includes: providing a gate and a spacer formed over a substrate; performing an implant that amorphizes the gate and a source/drain region defined by the spacer; removing the spacer; depositing a stress memorization layer over the in... | 07/20/2010 |
| 7759206 | Methods of forming semiconductor devices using embedded L-shape spacers A method of forming a semiconductor device that embeds an L-shaped spacer is provided. The method includes defining an L-shaped spacer on each side of a gate region of a substrate and embedding the L-shaped spacers in an oxide layer so that the oxide layer extends o... | 07/20/2010 |
| 7754573 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device. In one example embodiment of the present invention, a method for manufacturing a semiconductor device includes various steps. First, a gate pattern is formed on a substrate. Next, a first oxide layer is formed on th... | 07/13/2010 |
| 7745298 | Method of forming a via A method for forming a via includes forming a gate electrode over a semiconductor substrate, forming a source/drain region in the semiconductor substrate adjacent the gate electrode, forming a silicide region in the source/drain region, forming a post-silicide space... | 06/29/2010 |
| 7736983 | High threshold NMOS source-drain formation with As, P and C to reduce damage Pipe defects in n-type lightly doped drain (NLDD) regions and n-type source/drain (NDS) regions are associated with arsenic implants, while excess diffusion in NLDD and NSD regions is mainly due to phosphorus interstitial movement. Carbon implantation is commonly us... | 06/15/2010 |
| 7727845 | Ultra shallow junction formation by solid phase diffusion An ultra shallow junction (USJ) FET device and method for forming the same with improved control over SDE or LDD doped region interfaces to improve device performance and reliability is provided, the method including providing a semiconductor substrate; forming a ga... | 06/01/2010 |
| 7687364 | Low-k isolation spacers for conductive regions A multi-component low-k isolation spacer for a conductive region in a semiconductor structure is described. In one embodiment, a replacement isolation spacer process is utilized to enable the formation of a two-component low-k isolation spacer adjacent to a sidewall... | 03/30/2010 |
| 7659173 | Method for manufacturing insulated-gate type field effect transistor A poly-silicon layer is deposited on a surface of a substrate after forming a gate insulating film in an element hole of a field insulating film 12, and thereon a silicon oxide layer is formed by a thermal oxidation process. After patterning the silicon oxide... | 02/09/2010 |
| 7659174 | Method to enhance device performance with selective stress relief A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over ... | 02/09/2010 |
| 7618868 | Method of manufacturing field effect transistors using sacrificial blocking layers Provided are a more stable semiconductor integrated circuit device and a method of manufacturing the same. The method includes providing a semiconductor substrate comprising a first transistor region having a stacked structure of a first gate insulating layer and a ... | 11/17/2009 |
| 7611952 | Method of manufacturing semiconductor device having side wall spacers Gate insulating films 12A and 12B of different thickness are formed in element openings 16a and 16b in the isolation film 16 of a wafer 10. The gate insulating film 12B is the thinnest gate insulating fi... | 11/03/2009 |
| 7605044 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device including at least one step of: forming a transistor on and/or over a semiconductor substrate; forming silicide on and/or overa gate electrode and a source/drain region of the transistor; removing an uppermost oxide f... | 10/20/2009 |
| 7579250 | Method for reducing hot carrier effect of MOS transistor A semiconductor device structure is described, including a MOS transistor, a silicon-rich silicon nitride layer having a refractive index of about 2.00-2.30, and a dielectric layer. The silicon-rich silicon nitride layer is disposed between the MOS transistor and th... | 08/25/2009 |
| 7569457 | Method of fabricating semiconductor device An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of ... | 08/04/2009 |
| 7560353 | Methods of fabricating memory devices with memory cell transistors having gate sidewall spacers with different dielectric properties A memory device, such as a DRAM, SRAM or non-volatile memory device, includes a substrate, a gate electrode disposed on the substrate, and source and drain regions in the substrate adjacent respective first and second sidewalls of the gate electrode. First and secon... | 07/14/2009 |
| 7550357 | Semiconductor device and fabricating method thereof A semiconductor device with a low drain current in the off-state of LDD type accommodating high voltages is provided. On the thermal oxide film, a polysilicon film and a CVD oxide film, and a resist pattern are formed, then the CVD oxide film is side-etched for form... | 06/23/2009 |
| 7528047 | Self-aligned split gate memory cell and method of forming A method of forming a split gate memory device using a semiconductor layer includes patterning an insulating layer to leave a pillar thereof. A gate dielectric is formed over the semiconductor layer. A charge storage layer is formed over the gate dielectric and alon... | 05/05/2009 |
| 7517767 | Forming conductive stud for semiconductive devices Embodiments of the present invention provide a method of forming a conductive stud contacting a semiconductor device. The method includes forming a protective layer covering the semiconductor device; selectively etching an opening down through the protective layer r... | 04/14/2009 |
| 7517766 | Method of removing a spacer, method of manufacturing a metal-oxide-semiconductor transistor device, and metal-oxide-semiconductor transistor device A method of removing a spacer, a method of manufacturing a metal-oxide-semiconductor transistor device, and a metal-oxide-semiconductor transistor device, in which, before the spacer is removed, a protective layer is deposited on a spacer and on a material layer (su... | 04/14/2009 |
| 7514331 | Method of manufacturing gate sidewalls that avoids recessing A method of manufacturing a semiconductor device comprising removing a first oxide layer deposited over a semiconductor substrate, thereby exposing source and drain regions of the substrate. The first oxide layer is configured as an etch-stop for forming silicon nit... | 04/07/2009 |
