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| Number | Title | Issue Date |
| 8163622 | Method for angular doping of source and drain regions for odd and even NAND blocks A method for creating NAND flash memory. Source implantations are performed at a first implantation angle to areas between stacked gate structures of a NAND string. Drain implantations are performed at a second implantation angle to areas between the stacked gate st... | 04/24/2012 |
| 8084330 | Thin body semiconductor devices having improved contact resistance and methods for the fabrication thereof Embodiments of a method for fabricating a semiconductor device are provided. In one embodiment, the method includes the step of producing a partially-completed semiconductor device including a substrate, source/drain (S/D) regions, a channel region between the S/D r... | 12/27/2011 |
| 8034692 | Structure and method for manufacturing asymmetric devices A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate str... | 10/11/2011 |
| 8021949 | Method and structure for forming finFETs with multiple doping regions on a same chip A method for fabrication of features for an integrated circuit includes patterning a first semiconductor structure on a surface of a semiconductor device, and epitaxially growing semiconductor material on opposite sides of the first semiconductor structure to form f... | 09/20/2011 |
| 7919379 | Dielectric spacer removal The present invention relates to semiconductor devices, and more particularly to a process and structure for removing a dielectric spacer selective to a surface of a semiconductor substrate with substantially no removal of the semiconductor substrate. The method of ... | 04/05/2011 |
| 7902031 | Method for angular doping of source and drain regions for odd and even NAND blocks A method for creating NAND flash memory. Source implantations are performed at a first implantation angle to areas between stacked gate structures of a NAND string. Drain implantations are performed at a second implantation angle to areas between the stacked gate st... | 03/08/2011 |
| 7867866 | SOI FET with source-side body doping An SOI FET device with improved floating body is proposed. Control of the body potential is accomplished by having a body doping concentration next to the source electrode higher than the body doping concentration next to the drain electrode. The high source-side do... | 01/11/2011 |
| 7790562 | Method for angular doping of source and drain regions for odd and even NAND blocks Source implantations are performed at a first implantation angle to areas between stacked gate structures of a NAND string. Drain implantations are performed at a second implantation angle to areas between the stacked gate structures. The drain implantations create ... | 09/07/2010 |
| 7776702 | Method of fabricating high integrated semiconductor apparatus, and semiconductor apparatus fabricated thereby The present invention provides a method of fabricating a semiconductor apparatus including a vertical transistor and a semiconductor apparatus fabricated thereby which protect a pillar-shaped channel region to stabilize an operating characteristic of the semiconduct... | 08/17/2010 |
| 7772075 | Formation of a MOSFET using an angled implant A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS channel region is less than 80% of a distance between an outer boundary of an n+-type region an... | 08/10/2010 |
| 7749851 | Semiconductor device and method for fabricating semiconductor device According to the present invention, there is provided a semiconductor device including a first conductive type semiconductor substrate, a gate electrode formed over the semiconductor substrate via a gate insulator, a first conductive impurity region buried in the se... | 07/06/2010 |
| 7732290 | Carbon nanotube transistor process with transferred carbon nanotubes During fabrication of single-walled carbon nanotube transistor devices, a porous template with numerous parallel pores is used to hold the single-walled carbon nanotubes. The porous template or porous structure may be anodized aluminum oxide or another material. A g... | 06/08/2010 |
| 7704844 | High performance MOSFET A semiconductor structure which exhibits high device performance and improved short channel effects is provided. In particular, the present invention provides a metal oxide semiconductor field effect transistor (MOFET) that includes a low dopant concentration within... | 04/27/2010 |
| 7691713 | Method of manufacturing semiconductor device capable of suppressing impurity concentration reduction in doped channel region arising from formation of gate insulating film A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film (20) and a silicon nitride film (21) b... | 04/06/2010 |
| 7625802 | Semiconductor device having improved halo structures and a method of forming the halo structures of a semiconductor device A method of forming the halo structures of a field effect transistor is disclosed. The halo structures are formed by implanting ions of a dopant material into the substrate on which the transistor is to be formed, wherein the tilt angle of the ion beam with respect ... | 12/01/2009 |
| 7618867 | Method of forming a doped portion of a semiconductor and method of forming a transistor A method of forming a doped portion of a semiconductor substrate includes: defining a plurality of protruding portions on the substrate surface, the protruding portions having a minimum height; providing a pattern layer above the substrate surface; removing portions... | 11/17/2009 |
| 7595248 | Angled implantation for removal of thin film layers Embodiments of the invention provide a device with a reverse-tapered gate electrode and a gate dielectric layer with a length close to that of the gate length. In an embodiment, this may be done by altering portions of a blanket dielectric layer with one or more ang... | 09/29/2009 |
| 7572706 | Source/drain stressor and method therefor A method for forming a semiconductor device is provided. The method includes forming a gate structure overlying a substrate. The method further includes forming a sidewall spacer adjacent to the gate structure. The method further includes performing an angled implan... | 08/11/2009 |
| 7538003 | Method for fabricating MOS transistor A method for fabricating a metal oxide semiconductor (MOS) transistor comprises forming a source region of a first conductivity type and a drain region of the first conductivity type, which are separated from each other by a channel region, in upper regions of a sem... | 05/26/2009 |
| 7534690 | Non-volatile memory with asymmetrical doping profile Stacked gate structures for a NAND string are created on a substrate. Source implantations are performed at a first implantation angle to areas between the stacked gate structures. Drain implantations are performed at a second implantation angle to areas between the... | 05/19/2009 |
| 7494885 | Disposable spacer process for field effect transistor fabrication According to one exemplary embodiment, a method for forming a field effect transistor on a substrate comprises a step of forming disposable spacers adjacent to a gate stack situated on the substrate, where the disposable spacers comprise amorphous carbon. The dispos... | 02/24/2009 |
| 7449386 | Manufacturing method for semiconductor device to mitigate short channel effects A method of manufacturing a plurality of MOS transistors includes forming gate structures in first and second regions on a substrate and forming mask portions only between adjacent drain sides of the respective gate structures only in the first region. Dopant of a f... | 11/11/2008 |
| 7442614 | Silicon on insulator devices having body-tied-to-source and methods of making Methods of fabricating silicon on insulator devices having the body-tied-to-source are described. In an embodiment, a method of forming a transistor device comprises: providing a semiconductor topography comprising a gate conductor spaced above a semiconductor layer... | 10/28/2008 |
| 7402451 | Optimized transistor for imager device An imager device that has mitigated dark current leakage and punch-through protection. The transistor associated with the photoconversion device is formed with a single (i.e, one-sided) active area extension region on one side of the transistor gate opposite the pho... | 07/22/2008 |
| 7396713 | Structure and method for forming asymmetrical overlap capacitance in field effect transistors A method for forming asymmetric spacer structures for a semiconductor device includes forming a spacer layer over at least a pair of adjacently spaced gate structures disposed over a semiconductor substrate. The gate structures are spaced such that the spacer layer ... | 07/08/2008 |
| 7393752 | Semiconductor devices and method of fabrication A semiconductor having an ˜5V operational range, including a drain side enhanced gate-overlapped LDD (GOLD) and a source side halo implant region and well implant. A method in accordance with an embodiment of the invention comprises forming a gate electrode overlyi... | 07/01/2008 |
| 7378321 | Method for patterning a semiconductor component In a method for patterning a semiconductor component a first cover layer is applied to a first region and a second region of a semiconductor component being arranged in a semiconductor substrate. The first region is different from the second region. The first cover ... | 05/27/2008 |
| 7378323 | Silicide process utilizing pre-amorphization implant and second spacer A gate electrode is formed on a substrate with a gate insulating layer therebetween. A liner is then deposited on sidewalls of the gate electrode. Source/drain extensions are implanted into the substrate. A first spacer is then formed on the liner. Deep source/drain... | 05/27/2008 |
| 7374975 | Method of fabricating a transistor A method of forming a transistor reduces leakage current and hot carrier effects, and therefore improves current performance. The method of forming a transistor includes selectively etching the semiconductor substrate to form a substrate protrusion and expose a buri... | 05/20/2008 |
| 7361551 | Method for making an integrated circuit having an embedded non-volatile memory A method for forming a portion of a semiconductor device includes: patterning gate stack layers overlying a substrate into a gate stack; implanting dopant ions to form shallow source/drain extension implant regions in the substrate adjacent to the gate stack; oxidiz... | 04/22/2008 |
| 7358121 | Tri-gate devices and methods of fabrication The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite ... | 04/15/2008 |
| 7354833 | Method for improving threshold voltage stability of a MOS device This invention provides a method for improving threshold voltage stability of at least one metal-oxide-semiconductor (MOS) device. In one embodiment of the invention, at least one well is formed on a semiconductor substrate. A gate dielectric layer is formed on the ... | 04/08/2008 |
| 7351595 | Method for manufacturing semiconductor device In a manufacturing method for a semiconductor device, a main body wafer having an interlayer insulating film is formed, and a monitor wafer on which a monitor element is formed is provided. Characteristics of the main body wafer are copied onto the monitor element b... | 04/01/2008 |
| 7351637 | Semiconductor transistors having reduced channel widths and methods of fabricating same A method of forming a channel in a semiconductor device including forming an opening in a masking layer to expose a portion of an underlying semiconductor layer through the opening is provided. The method further includes disposing a screening layer and implanting a... | 04/01/2008 |
| 7351627 | Method of manufacturing semiconductor device using gate-through ion implantation Disclosed herein is a method of manufacturing a semiconductor device via gate-through ion implantation, comprising forming a gate stack on a semiconductor substrate and performing ion implantation for control of the threshold voltage and junction ion implantation fo... | 04/01/2008 |
| 7348221 | Process for manufacturing a semiconductor device, a semiconductor device and a high-frequency circuit A process for manufacturing a semiconductor device, provides that a silicide layer is formed, an amorphous semiconductor layer is applied both to the silicide layer and to an open monocrystalline semiconductor region, adjacent to the silicide layer, and during a sub... | 03/25/2008 |
| 7345296 | Nanotube transistor and rectifying devices Single-walled carbon nanotube transistor and rectifying devices, and associated methods of making such devices include a porous structure for the single-walled carbon nanotubes. The porous structure may be anodized aluminum oxide or another material. Electrodes for ... | 03/18/2008 |
| 7342276 | Method and apparatus utilizing monocrystalline insulator A semiconductor device, including: a semiconductor material; a conductive element; and a substantially monocrystalline insulator disposed between the semiconductor material and the conductive eleme... | 03/11/2008 |
| 7342266 | Field effect transistors with dielectric source drain halo regions and reduced miller capacitance A field effect transistor (FET) device includes a gate conductor and gate dielectric formed over an active device area of a semiconductor substrate. A drain region is formed in the active device area of the semiconductor substrate, on one side of the gate conductor,... | 03/11/2008 |
| 7338876 | Method for manufacturing a semiconductor device A method for forming a semiconductor memory device includes the steps of: implanting a dopant in a semiconductor substrate; heat treating the semiconductor substrate in an oxidizing ambient to diffuse the dopant for forming diffused regions in the semiconductor subs... | 03/04/2008 |
