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| Number | Title | Issue Date |
| 8183117 | Device layout in integrated circuits to reduce stress from embedded silicon-germanium An integrated circuit including one or more transistors in which source and drain regions are formed as embedded silicon-germanium (eSiGe). Guard ring structures in the integrated circuit are formed in single-crystal silicon, rather than in eSiGe. In one example, p-... | 05/22/2012 |
| 8183118 | Method for fabricating MOS transistor The invention discloses a method for fabricating a MOS transistor. A substrate having thereon a gate structure is provided. A silicon nitride layer is deposited on the gate structure. A dry etching process is then performed to define a silicon nitride spacer on each... | 05/22/2012 |
| 8178414 | NMOS architecture involving epitaxially-grown in-situ N-type-doped embedded eSiGe:C source/drain targeting An NMOS transistor is formed with improved manufacturability. An embodiment includes forming N-type doped embedded silicon germanium containing carbon (eSiGe:C) in source/drain regions of a substrate, and amorphizing the eSiGe:C. The use of eSiGe:C provides a reduct... | 05/15/2012 |
| 8168503 | Method for forming an SOI schottky source/drain device to control encroachment and delamination of silicide A method of fabricating a Schottky field effect transistor is provided that includes providing a substrate having at least a first semiconductor layer overlying a dielectric layer, wherein the first semiconductor layer has a thickness of less than 10.0 nm. A gate st... | 05/01/2012 |
| 8153494 | Nanowire MOSFET with doped epitaxial contacts for source and drain A FET structure with a nanowire forming the FET channel, and doped source and drain regions formed by radial epitaxy from the nanowire body is disclosed. A top gated and a bottom gated nanowire FET structures are discussed. The source and drain fabrication can use e... | 04/10/2012 |
| 8138055 | Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material ... | 03/20/2012 |
| 8138053 | Method of forming source and drain of field-effect-transistor and structure thereof Embodiments of the invention provide a method of forming a field-effect-transistor (FET). The method includes implanting one or more n-type dopants to create one or more implanted regions with at least a portion of the implanted regions being designated as regions f... | 03/20/2012 |
| 8138054 | Enhanced field effect transistor An enhanced FET capable of controlling current above and below a gate of the FET. The FET is formed on a semiconductor substrate. A source and drain are formed in the substrate (or in a well in the substrate). A first epitaxial layer of similar doping to the source ... | 03/20/2012 |
| 8129247 | Omega shaped nanowire field effect transistors A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire on a semiconductor substrate, forming a first gate structure on a first portion of the nanowire, forming a first protective spacer adjacent to sidewalls of the first gat... | 03/06/2012 |
| 8124487 | Method for enhancing tensile stress and source/drain activation using Si:C A method is disclosed for enhancing tensile stress in the channel region of a semiconductor structure. The method includes performing a series of ion implantation steps at predetermined implant energies to implant carbon ions deep within the semiconductor structure ... | 02/28/2012 |
| 8114747 | Method for creating 3-D single gate inverter A 3-D (Three Dimensional) inverter having a single gate electrode. The single gate electrode has a first gate dielectric between the gate electrode and a body of a first FET (Field Effect transistor) of a first doping type, the first FET having first source/drain re... | 02/14/2012 |
| 8097517 | Method for manufacturing semiconductor device with improved short channel effect of a PMOS and stabilized current of a NMOS The present invention relates to a semiconductor device which is capable of simultaneously improving a short channel effect of a PMOS and the current of an NMOS and a method for manufacturing the same. The semiconductor device includes first and second gates formed ... | 01/17/2012 |
| 8093130 | Method of manufacturing a semiconductor device having raised source and drain of differing heights This semiconductor device has an MOS transistor equipped with a gate electrode formed on a semiconductor substrate, a source region next to one side of the gate electrode, and a drain region next to another side of the gate electrode, wherein an upper end of the sou... | 01/10/2012 |
| 8062947 | Semiconductor device and method of manufacturing the same The present invention relates to a method of manufacturing a semiconductor device having a shared contact for connection between a source/drain region and a gate electrode. After formation of a gate electrode via a gate insulating film on a semiconductor substrate, ... | 11/22/2011 |
| 8062948 | Method of fabricating transistor for semiconductor device A method of fabricating a transistor in a semiconductor device includes forming a gate structure over a substrate, forming a first trench by etching the substrate on either side of the gate structure to a first depth, ion-implanting dopants of a first conductivity t... | 11/22/2011 |
| 8058133 | Method of fabrication of metal oxide semiconductor field effect transistor A method of fabrication of a metal oxide semiconductor field effect transistor includes first providing a substrate on which a gate structure is formed. Afterwards, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gat... | 11/15/2011 |
| 8043920 | finFETS and methods of making same A method of fabricating and a structure of a merged multi-fin finFET. The method includes forming single-crystal silicon fins from the silicon layer of an SOI substrate having a very thin buried oxide layer and merging the end regions of the fins by growing vertical... | 10/25/2011 |
| 8043919 | Method of fabricating semiconductor device A method of fabricating a semiconductor device is provided. A gate structure is formed on a substrate and then a first spacer is formed at a sidewall of the gate structure. Next, recesses are respectively formed in the substrate at two sides of the first spacer. The... | 10/25/2011 |
| 8039350 | Methods of fabricating MOS transistors having recesses with elevated source/drain regions Methods of fabricating metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions are provided. The MOS transistors formed by these methods may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions ... | 10/18/2011 |
| 8026144 | Method for manufacturing semiconductor device In a semiconductor device having a raised source and drain structure, in forming a raised region by etching, etching of an island-like semiconductor film which is an active layer is inhibited. In a method for manufacturing a semiconductor device, an insulating film ... | 09/27/2011 |
| 8017487 | Method to control source/drain stressor profiles for stress engineering A strained channel transistor structure and methods of forming a semiconductor device are presented. The transistor structure includes a strained channel region having a first semiconductor material with a first natural lattice constant. A gate dielectric layer over... | 09/13/2011 |
| 8012839 | Method for fabricating a semiconductor device having an epitaxial channel and transistor having same A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a l... | 09/06/2011 |
| 8012840 | Semiconductor device and method of manufacturing semiconductor device A semiconductor device includes a side wall spacer formed on the side surface of a gate electrode formed on the upper side of a semiconductor substrate with a gate insulation film therebetween, extension regions built up on the semiconductor substrate, and source/dr... | 09/06/2011 |
| 8008157 | CMOS device with raised source and drain regions A method of forming a semiconductor structure includes forming a PMOS device and an NMOS device. The step of forming the PMOS device includes forming a first gate stack on a semiconductor substrate; forming a first offset spacer on a sidewall of the first gate stack... | 08/30/2011 |
| 8003472 | Method of manufacturing semiconductor device When transistors having different gate lengths are formed on one substrate and an ESD structure is applied to at least a transistor having longer gate length, a method including: depositing a gate insulating film and a gate electrode material layer on the substrate;... | 08/23/2011 |
| 8003470 | Strained semiconductor device and method of making the same In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a side... | 08/23/2011 |
| 8003471 | Formation of a super steep retrograde channel Systems and methods for raised source/drain with super steep retrograde channel. In accordance with a first embodiment of the present invention, in one embodiment, a semiconductor device comprises a substrate comprising a surface and a gate oxide disposed above the ... | 08/23/2011 |
| 7994014 | Semiconductor devices having faceted silicide contacts, and related fabrication methods The disclosed subject matter relates to semiconductor transistor devices and associated fabrication techniques that can be utilized to form silicide contacts having an increased effective size, relative to conventional silicide contacts. A semiconductor device fabri... | 08/09/2011 |
| 7989298 | Transistor having V-shaped embedded stressor A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a monocrystalline semiconductor region and forming first spacers on exposed walls of the gate conductor. Using the gat... | 08/02/2011 |
| 7989299 | Semiconductor device, method of manufacturing the same, and method of evaluating semiconductor device A semiconductor device has: a silicon (semiconductor) substrate; a gate insulating film and a gate electrode, which are formed on the silicon substrate in this order; and source/drain material layers formed in recesses (holes) in the silicon substrate, the recesses ... | 08/02/2011 |
| 7989297 | Asymmetric epitaxy and application thereof The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming a gate structure on top of a semiconductor substrate, the gate structure including a gate stack and spacers adjacent to sidewalls of the gate stack, a... | 08/02/2011 |
| 7989296 | Semiconductor device and method of manufacturing same A semiconductor device and related method of manufacture are disclosed. The semiconductor device comprises a gate electrode formed on a semiconductor substrate, an active region containing spaces formed below the gate electrode, a channel region formed between the g... | 08/02/2011 |
| 7981751 | Structure and method for fabricating self-aligned metal contacts A semiconductor structure including at least one transistor is provided which has a stressed channel region that is a result of having a stressed layer present atop a gate conductor that includes a stack comprising a bottom polysilicon (polySi) layer and a top metal... | 07/19/2011 |
| 7981750 | Methods of fabrication of channel-stressed semiconductor devices In one aspect, a method of fabricating a semiconductor device is provided. The method includes forming at least one capping layer over epitaxial source/drain regions of a PMOS device, forming a stress memorization (SM) layer over the PMOS device including the at lea... | 07/19/2011 |
| 7968413 | Methods for forming a transistor Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate ... | 06/28/2011 |
| 7968414 | Semiconductor device and production method thereof A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially ... | 06/28/2011 |
| 7960237 | Structure and method for mosfet with reduced extension resistance The present invention provides a method in which a low-resistance connection between the MOS channel and silicided source/drain regions is provided that has an independence from the extension ion implant process as well as device overlap capacitance. The method of t... | 06/14/2011 |
| 7960236 | Phosphorus containing Si epitaxial layers in N-type source/drain junctions Methods for formation of epitaxial layers containing n-doped silicon are disclosed. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devi... | 06/14/2011 |
| 7955936 | Semiconductor fabrication process including an SiGe rework method A method for fabricating a semiconductor device includes forming an SiGe region. The SiGe region can be an embedded source and drain region, or a compressive SiGe channel layer, or other SiGe regions within a semiconductor device. The SiGe region is exposed to an SC... | 06/07/2011 |
| 7951680 | Integrated circuit system employing an elevated drain A method for manufacturing an integrated circuit system that includes: providing a substrate including an active device; forming a drift region in the substrate, the drift region bounded in part by a top surface of the substrate and spaced apart from a source; and f... | 05/31/2011 |
