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| Number | Title | Issue Date |
| 8183061 | High density spin-transfer torque MRAM process A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascen... | 05/22/2012 |
| 8178362 | Electronically scannable multiplexing device An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The d... | 05/15/2012 |
| 8178361 | Magnetic sensor and manufacturing method therefor There is provided a small-size magnetic sensor for detecting the intensity of a magnetic field in three axial directions, in which a plurality of giant magnetoresistive elements are formed on a single semiconductor substrate. A thick film is formed on the semiconduc... | 05/15/2012 |
| 8178363 | MRAM with storage layer and super-paramagnetic sensing layer An MRAM is disclosed that has a MTJ comprised of a ferromagnetic layer with a magnetization direction along a first axis, a super-paramagnetic (SP) free layer, and an insulating layer formed therebetween. The SP free layer has a remnant magnetization that is substan... | 05/15/2012 |
| 8173446 | Method of producing an integrated micromagnet sensor assembly A method of integrating a permanent bias magnet within a magnetoresistance sensor comprising depositing an alternating pattern of a metal material and a semiconductor material on or within a surface of an insulating substrate; depositing a mask on the surface of the... | 05/08/2012 |
| 8173447 | Magnetoresistive element and magnetic memory A magnetoresistive element includes: a magnetization free layer having a first plane and a second plane located on the opposite side from the first plane, and having a variable magnetization direction; a magnetization pinned layer provided on the first plane side of... | 05/08/2012 |
| 8168448 | Ferroelectric register, and method for manufacturing capacitor of the same The present invention discloses a ferroelectric register and a method for manufacturing a capacitor of the same. The ferroelectric register is configured to reduce probability of data storage failure due to a weak state capacitor, by connecting a plurality of capaci... | 05/01/2012 |
| 8168449 | Template-registered diblock copolymer mask for MRAM device formation A method for fabricating a magnetoresistive random access memory (MRAM) includes forming a mask over a magnetic layer; forming a template on the mask; applying a diblock copolymer to the template; curing the diblock copolymer to form a first plurality of uniform sha... | 05/01/2012 |
| 8163569 | Magnetic memory devices and methods of forming the same Provided are a magnetic memory device and a method of forming the same. The method may include forming a pinning pattern on a substrate; forming a first interlayer insulating layer that exposes the pinning pattern on the substrate; forming a pinned layer, a tunnelin... | 04/24/2012 |
| 8158445 | Methods of forming pattern structures and methods of manufacturing semiconductor devices using the same Methods of forming pattern structures and methods of manufacturing memory devices using the same are provided, the methods of forming pattern structures include forming an etching object layer on a substrate and performing a plasma reactive etching process on the et... | 04/17/2012 |
| 8153449 | Microwave integrated circuit package and method for forming such package A method for packaging a semiconductor device. The method includes: providing a dielectric layer over the semiconductor device; determining patterns and placement of material on the dielectric layer to provide a predetermined magnetic or electric effect for the devi... | 04/10/2012 |
| 8153447 | Nonvolatile ferroelectric perpendicular electrode cell, FeRAM having the cell and method for manufacturing the cell A nonvolatile ferroelectric perpendicular electrode cell comprises a ferroelectric capacitor and a serial PN diode switch. The ferroelectric capacitor includes a word line perpendicular electrode as a first electrode and a storage perpendicular electrode as a second... | 04/10/2012 |
| 8153448 | Manufacturing method of a semiconductor device There are provided a capacitor lower electrode formed on an adhesive layer, whose surface roughness is 0.79 nm or less, and having a (111) orientation that is inclined from a perpendicular direction to an upper surface of a substrate by 2.3° or less, a ferroelectri... | 04/10/2012 |
| 8148174 | Magnetic tunnel junction (MTJ) formation with two-step process A method of manufacturing a magnetic memory element includes the steps of performing a first etching an oxide layer is etched, using a first photo-resist, the oxide layer formed on top of a contact layer that is formed on top of a magneto tunnel junction (MTJ), depo... | 04/03/2012 |
| 8133745 | Method of magnetic tunneling layer processes for spin-transfer torque MRAM A method for forming a MTJ in a STT-MRAM is disclosed in which the easy-axis CD is determined independently of the hard-axis CD. One approach involves two photolithography steps and two etch steps to form a post in a hard mask which is transferred through a MTJ stac... | 03/13/2012 |
| 8129200 | Nonvolatile ferroelectric memory device and method for manufacturing the same A nonvolatile ferroelectric memory device includes a plurality of unit cells. Each of the unit cells includes a cell capacitor and a cell transistor. The cell capacitor includes a storage node, a ferroelectric layer, and a plate line. The cell capacitors of more tha... | 03/06/2012 |
| 8124425 | Method for manufacturing magnetic memory chip device A method for manufacturing a magnetic memory chip device comprises the steps of: writing information in each of a plurality of magnetic memory chips formed on a silicon wafer; adhering a high magnetic permeability plate on a back face of the silicon wafer after writ... | 02/28/2012 |
| 8124426 | Tunnel junction via A method for forming a tunnel junction (TJ) circuit, the method includes forming a bottom wiring layer; forming a plurality of TJs contacting the bottom wiring layer; forming a plurality of tunnel junction vias (TJVs) simultaneously with the formation of the plurali... | 02/28/2012 |
| 8119425 | Method of forming magnetic memory device There are provided a magnetic memory device and a method of forming the magnetic memory device. The method of forming the magnetic memory device includes sequentially forming a first magnetic conductor, a tunnel barrier layer, and a second magnetic conductor on a su... | 02/21/2012 |
| 8119424 | Electronic device including a magneto-resistive memory device and a process for forming the electronic device A process of forming an electronic device can include forming a stack including a tunnel barrier layer. The tunnel barrier layer can have a ratio of the metal atoms to oxygen atoms of greater than a stoichiometric ratio, wherein the ratio has a particular value. The... | 02/21/2012 |
| 8114684 | Vertical hall effect sensor with current focus A complementary metal oxide semiconductor (CMOS) sensor system in one embodiment includes a doped substrate, a doped central island extending downwardly within the doped substrate from an upper surface of the doped substrate, and a first doped outer island extending... | 02/14/2012 |
| 8110411 | Semiconductor device and manufacturing method thereof The present invention provides a semiconductor device which is characterized as follows. The semiconductor device includes: an interlayer insulating film formed above a semiconductor substrate and provided with a hole above an impurity diffusion region; a conductive... | 02/07/2012 |
| 8105850 | Process for selectively patterning a magnetic film structure Processes for selectively patterning a magnetic film structure generally include selectively etching an exposed portion of a freelayer disposed on a tunnel barrier layer by a wet process, which includes exposing the freelayer to an etchant solution comprising at lea... | 01/31/2012 |
| 8093071 | Semiconductor device and method of manufacturing the same According to the present invention, a method of fabricating a semiconductor device is provided including forming a first interlayer insulating film 11, a crystalline conductive film 21, a first conductive film 23, a ferroelectric film 24 ... | 01/10/2012 |
| 8093070 | Method for leakage reduction in fabrication of high-density FRAM arrays A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroele... | 01/10/2012 |
| 8080433 | Method for detaching layers with low magnetic permeability A method for detaching a first material layer from a second material layer includes following steps: forming a high-magnetic-permeability material layer on a first material layer comprised of low-magnetic-permeability material; removing a portion of the high-magneti... | 12/20/2011 |
| 8080432 | High performance MTJ element for STT-RAM and method for making the same A method of forming a STT-MTJ MRAM cell that utilizes transfer of spin angular momentum as a mechanism for changing the magnetic moment direction of a free layer. The device includes an IrMn pinning layer, a SyAP pinned layer, a naturally oxidized, crystalline MgO t... | 12/20/2011 |
| 8071396 | Embedded phase-change memory and method of fabricating the same An embedded memory required for a high performance, multifunction SOC, and a method of fabricating the same are provided. The memory includes a bipolar transistor, a phase-change memory device and a MOS transistor, adjacent and electrically connected, on a substrate... | 12/06/2011 |
| 8067250 | Ferroelectric memory device and method of manufacturing the same A method of manufacturing a ferroelectric memory device includes: forming a hydrogen barrier film which covers a ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode, wherein a thickness of an area of the hydrogen barrier... | 11/29/2011 |
| 8062909 | MRAM with storage layer and super-paramagnetic sensing layer An MRAM is disclosed that has a MTJ comprised of a ferromagnetic layer with a magnetization direction along a first axis, a super-paramagnetic (SP) free layer, and an insulating layer formed therebetween. The SP free layer has a remnant magnetization that is substan... | 11/22/2011 |
| 8058080 | Method of manufacturing a magnetic random access memory, method of manufacturing an embedded memory, and template A magnetic material of a magnetoresistive element is formed on a lower electrode. An upper electrode is formed on the magnetic material. A resist for nano-imprint lithography is formed on the upper electrode. A first pattern or a second pattern is formed in the resi... | 11/15/2011 |
| 8053252 | Mitigation of edge degradation in ferroelectric memory devices through plasma etch clean A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The ... | 11/08/2011 |
| 8053251 | Temperature-compensated ferroelectric capacitor device, and its fabrication A temperature-compensated capacitor device has ferroelectric properties and includes a ferroelectric capacitor using a ferroelectric material such as a metal oxide ferroelectric material, a negative-temperature-variable capacitor using a negative-temperature-coeffic... | 11/08/2011 |
| 8048686 | Production of a device comprising magnetic structures formed on one and the same substrate and having respective different magnetization orientations The invention relates to a method for producing a device comprising magnetic blocks magnetized in different directions, comprising steps of: a) forming, in a stack of one or more layers of at least one antiferromagnetic material and one or more layers of at l... | 11/01/2011 |
| 8048684 | Structure and method for manipulating spin quantum state through dipole polarization switching Disclosed herein is a structure and method for manipulating a spin state, regarded as important in the field of spintronics, by which the distribution of spin-up and spin-down states of carriers in a hybrid double quantum disk structure, composed of a diluted magnet... | 11/01/2011 |
| 8048685 | Magnetic RAM A memory element for a magnetic RAM, having a first magnetic portion in a first recess of a first insulating layer; and a non-magnetic portion and a second magnetic portion in a second recess of a second insulating layer covering the first insulating layer, the seco... | 11/01/2011 |
| 8043869 | Magnetic memory device and method of fabricating the same A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the rea... | 10/25/2011 |
| 8034637 | Techniques for coupling in semiconductor devices Techniques for exchange coupling of magnetic layers in semiconductor devices are provided. In one aspect, a semiconductor device is provided. The device comprises at least two magnetic layers, and a spacer layer formed between the magnetic layers, the spacer layer b... | 10/11/2011 |
| 8026112 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device includes: forming first conductive layer on semiconductor substrate; forming a magnetic film on the first conductive layer; forming second conductive layer on the magnetic film; forming a first mask layer on the secon... | 09/27/2011 |
| 8026111 | Dielectric enhancements to chip-to-chip capacitive proximity communication A method for improving signal levels between capacitively-coupled chips in proximity communication (PxC) includes depositing a high permittivity dielectric material layer over a signal pad of a first chip, and placing a second chip in close proximity to the first ch... | 09/27/2011 |
