Class 438/299 - Self-aligned

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process for making an insulated gate field effect transistor
No. of patents: 707
Last issue date: 04/03/2012

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Number	Title	Issue Date
8148227	Method for providing a self-aligned conductive structure An embodiment according to the present invention comprises a method for providing a self-aligned conductive structure comprising providing a first structure on a surface, wherein the first structure comprises a first and a second layer, and providing an intermediate...	04/03/2012
8138052	Metal high dielectric constant transistor with reverse-T gate A transistor is provided. The transistor includes a silicon layer including a source region and a drain region. A gate stack is disposed on the silicon layer between the source region and the drain region. The gate stack comprises a first layer of a high dielectric ...	03/20/2012
8088665	Method of forming self-aligned low resistance contact layer Embodiments of the present invention describe a method of fabricating low resistance contact layers on a semiconductor device. The semiconductor device comprises a substrate having source and drain regions. The substrate is alternatingly exposed to a first precursor...	01/03/2012
8076209	Methods for fabricating MOS devices having highly stressed channels Methods for forming a semiconductor device comprising a silicon-comprising substrate are provided. One exemplary method comprises depositing a polysilicon layer overlying the silicon-comprising substrate, amorphizing the polysilicon layer, etching the amorphized pol...	12/13/2011
8058132	Method of fabricating flash memory device The present disclosure relates to a method of fabricating a flash memory device. According to the present disclosure, a hard mask layer to which surface roughnesses have been transferred by a metal silicide layer, including the surface roughness, is polished before ...	11/15/2011
8048751	Method for producing a field effect device having self-aligned electrical connections with respect to the gate electrode A gate dielectric, an insulating layer and an etching mask are formed on substrate. The etching mask delineates at least the gate electrode and the source and drain contacts and the source, drain and gate output lines of the first metal level of a field effect devic...	11/01/2011
7915128	High voltage semiconductor devices A transistor suitable for high-voltage applications and a method of manufacture is provided. A first device is formed by depositing a dielectric layer and a conductive layer over a substrate. A hard mask is deposited over the conductive layer and patterned using pho...	03/29/2011
7915129	Method of fabricating high-voltage metal oxide semiconductor transistor devices A process of fabricating a transistor employs a relatively thicker sacrificial nitride layer that reduces the time and cost associated with chemical-mechanical polish (CMP) processes by reducing the topography associated with the transistor. The process includes for...	03/29/2011
7892930	Method to improve transistor tox using SI recessing with no additional masking steps A method of forming a transistor device is provided wherein a gate structure is formed over a semiconductor body of a first conductivity type. The gate structure is formed comprising a protective cap thereover and defining source/drain regions laterally adjacent the...	02/22/2011
7888220	Self-aligned insulating etchstop layer on a metal contact A semiconductor device comprising a substrate having a transistor that includes a metal gate structure; a first oxide layer formed over the substrate; a silane layer formed on the first oxide layer; and a non-conductive metal oxide layer grown on the metal gate stru...	02/15/2011
7883978	Semiconductor device and method for manufacturing the same Disclosed are a semiconductor device and a method for manufacturing the same. The method includes forming a gate layer on a semiconductor substrate; forming a first oxide layer on the semiconductor substrate; forming a second oxide layer on the first oxide layer; ex...	02/08/2011
7875519	Metal gate structure and method of manufacturing same A method of manufacturing a metal gate structure includes providing a substrate (110) having formed thereon a gate dielectric (120), a work function metal (130) adjacent to the gate dielectric, and a gate metal (140) adjacent to the work ...	01/25/2011
7867863	Method for forming self-aligned source and drain contacts using a selectively passivated metal gate A transistor structure includes a semiconductor substrate with a first surface, a diffusion region at the first surface of the substrate, a sacrificial gate formed on the diffusion region, and insulating side walls formed adjacent to the sacrificial gate. A metal ga...	01/11/2011
7858481	Method for fabricating transistor with thinned channel A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process. ...	12/28/2010
7842578	Method for fabricating MOS devices with a salicided gate and source/drain combined with a non-silicide source drain regions A method for fabricating an integrated circuit device, e.g., CMOS image sensor. The method includes providing a semiconductor substrate, which has a first device region and a second device region. The method forms a gate polysilicon layer overlying the first and sec...	11/30/2010
7838371	Method of manufacturing a FET gate A method of manufacturing a FET gate with a plurality of materials includes depositing a dummy region 8, and then forming a plurality of metallic layers 16, 18, 20 on gate dielectric 6 by conformally depositing a layer of each metallic layer and...	11/23/2010
7790561	Gate sidewall spacer and method of manufacture therefor The present invention provides a method for manufacturing a semiconductor device, a semiconductor device, and a method for manufacturing an integrated circuit including a semiconductor device. The method for manufacturing the semiconductor device, without limitation...	09/07/2010
7772074	Method of forming conformal silicon layer for recessed source-drain Processes for non-selectively forming one or more conformal silicon-containing epitaxial layers on recess corners are disclosed. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semico...	08/10/2010
7767534	Methods for fabricating MOS devices having highly stressed channels Methods for forming a semiconductor device comprising a silicon-comprising substrate are provided. One exemplary method comprises depositing a polysilicon layer overlying the silicon-comprising substrate, amorphizing the polysilicon layer, etching the amorphized pol...	08/03/2010
7736981	Metal high dielectric constant transistor with reverse-T gate A transistor is provided. The transistor includes a silicon layer including a source region and a drain region. A gate stack is disposed on the silicon layer between the source region and the drain region. The gate stack comprises a first layer of a high dielectric ...	06/15/2010
7723195	Method of forming a field effect transistor A method of forming a field effect transistor comprises providing a substrate comprising a biaxially strained layer of a semiconductor material. A gate electrode is formed on the biaxially strained layer of semiconductor material. A raised source region and a raised...	05/25/2010
7723196	Damascene gate field effect transistor with an internal spacer structure A MOSFET is disclosed that comprises a channel between a source extension and a drain extension, a dielectric layer over the channel, a gate spacer structure formed on a peripheral portion of the dielectric layer, and a gate formed on a non-peripheral portion of the...	05/25/2010
7700449	Forming ESD diodes and BJTs using FinFET compatible processes A method of forming an electrostatic discharging (ESD) device includes forming a first and a second semiconductor fin over a substrate and adjacent to each other; epitaxially growing a semiconductor material on the first and the second semiconductor fins, wherein a ...	04/20/2010
7696050	Method of manufacturing semiconductor device carrying out ion implantation before silicide process An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drai...	04/13/2010
7659171	Methods and structure for forming self-aligned borderless contacts for strain engineered logic devices A method for forming a borderless contact for a semiconductor FET (Field Effect Transistor) device, the method comprising, forming a gate conductor stack on a substrate, forming spacers on the substrate, such that the spacers and the gate conductor stack partially d...	02/09/2010
7625800	Method of fabricating MOS transistor A method for fabricating a MOS transistor is suitable for modifying the configuration of a gate electrode. The method includes coating a first oxide layer on a semiconductor substrate and removing a predetermined width of the first oxide layer; forming an LDD region...	12/01/2009
7615454	Embedded stressed nitride liners for CMOS performance improvement The present invention provides a semiconducting device including a gate region positioned on a mesa portion of a substrate; and a nitride liner positioned on the gate region and recessed surfaces of the substrate adjacent to the gate region, the nitride liner provid...	11/10/2009
7601599	Semiconductor device and method for manufacturing the same A method for manufacturing a semiconductor device includes the steps of (a) forming a first insulating film pattern, which has a first portion and a second portion separated from the first portion through a first space, above a semiconductor substrate, (b) selective...	10/13/2009
7569455	Manufacturing method of semiconductor device A manufacturing method of a CMOS semiconductor device includes using, in an nMOS, spike RTA (first annealing) together with ultra-rapid rising/falling temperature annealing (second annealing) whose temperature increase/decrease rate is higher than that of the spike ...	08/04/2009
7566624	Method for the production of transistor structures with LDD A method for producing a transistor structure with a lightly doped drain (LDD) includes structuring a gate electrode on a gate dielectric. The method also includes etching the semiconductor body or substrate to form sloping sidewails on regions adjacent to the gate ...	07/28/2009
7544575	Dual metal silicide scheme using a dual spacer process A semiconductor process and apparatus provide a polysilicon structure (10) and source/drain regions (12, 14) formed adjacent thereto in which a dual silicide scheme is used to form first silicide regions in the polysilicon, source and drain regions (	06/09/2009
7439143	Flash memory device and method of manufacturing the same Disclosed is a flash memory device. The flash memory device includes a plurality of trench lines in an isolation region of a semiconductor device, a common source region along a word line (WL) direction under a surface portion of the semiconductor substrate, a plura...	10/21/2008
7435659	Method for manufacturing a semiconductor device having an alignment feature formed using an N-type dopant and a wet oxidation process The present invention provides a method for manufacturing a semiconductor device having an alignment feature. The method for manufacturing the semiconductor device, among other steps, may include implanting an n-type dopant into a substrate thereby forming an implan...	10/14/2008
7429517	CMOS transistor using high stress liner layer A MOS transistor structure comprising a gate dielectric layer (30), a gate electrode (40), and source and drain regions (70) are formed in a semiconductor substrate (10). First second and third dielectric layers (110), (120)...	09/30/2008
7425490	Reducing reactions between polysilicon gate electrodes and high dielectric constant gate dielectrics In a metal gate replacement process, a gate electrode stack may be formed of a dielectric covered by a sacrificial metal layer covered by a polysilicon gate electrode. In subsequent processing of the source/drains, high temperature steps may be utilized. The sacrifi...	09/16/2008
7422949	High voltage transistor and method of manufacturing the same The present invention relates to a high voltage transistor and method of manufacturing the same. The high voltage transistor includes: a channel region which is formed in a semiconductor substrate; a gate insulating film which is formed on the channel region of the ...	09/09/2008
7419892	Semiconductor devices including implanted regions and protective layers and methods of forming the same Methods of forming a semiconductor device include forming a protective layer on a semiconductor layer, implanting ions having a first conductivity type through the protective layer into the semiconductor layer to form an implanted region of the semiconductor layer, ...	09/02/2008
7416968	Methods of forming field effect transistors having metal silicide gate electrodes Methods of forming field effect transistors according to embodiments of the invention include forming a conductive gate electrode (e.g., polysilicon gate electrode) on a semiconductor substrate and forming a first metal layer on the conductive gate electrode. This f...	08/26/2008
7413956	Semiconductor device manufacturing method Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes a semiconductor substrate, in which active and inactive regions are separated by a field oxidation film; source/drain junctions contacting the field oxida...	08/19/2008
7405130	Method of manufacturing a semiconductor device with a notched gate electrode A silicon nitride film having a thickness of 3 nm or less is formed on the surfaces of a P-well and N-well, as well as on the upper and side surfaces of a gate electrode, in which the silicon nitride film can be formed, for example, by exposing the surface of the P-...	07/29/2008

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Class 438/299 - Self-aligned