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| Number | Title | Issue Date |
| 8163621 | High performance LDMOS device having enhanced dielectric strain layer An LDMOS device includes a substrate having a surface and a gate electrode overlying the surface and defining a channel region in the substrate below the gate electrode. A drain region is spaced apart from the channel region by an isolation region. The isolation reg... | 04/24/2012 |
| 8114746 | Method for forming double gate and tri-gate transistors on a bulk substrate Three-dimensional transistor structures such as FinFETS and tri-gate transistors may be formed on the basis of an enhanced masking regime, thereby enabling the formation of drain and source areas, the fins and isolation structures in a self-aligned manner within a b... | 02/14/2012 |
| 8088664 | Method of manufacturing integrated deep and shallow trench isolation structures A method of forming an integrated deep and shallow trench isolation structure comprises depositing a hard mask on a film stack having a plurality of layers formed on a substrate such that the hard mask is deposited on a furthermost layer from the substrate, imprinti... | 01/03/2012 |
| 8076208 | Method for forming transistor with high breakdown voltage using pitch multiplication technique Transistors are formed using pitch multiplication. Each transistor includes a source region and a drain region connected by strips of active area material separated by shallow trench isolaton structures. The shallow trench isolaton structures are formed by dielectri... | 12/13/2011 |
| 8053322 | Epitaxial deposition-based processes for reducing gate dielectric thinning at trench edges and integrated circuits therefrom A method of fabricating an integrated circuit (IC) and ICs therefrom including a plurality of Metal Oxide Semiconductor (MOS) transistors having reduced gate dielectric thinning and corner sharpening at the trench isolation/semiconductor edge for gate dielectric lay... | 11/08/2011 |
| 8043918 | Semiconductor device and its manufacturing method To manufacture in high productivity a semiconductor device capable of securely achieving element isolation by a trench-type element isolation and capable of effectively preventing potentials of adjacent elements from affecting other nodes, a method of manufacturing ... | 10/25/2011 |
| 8043917 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device includes forming a silicon substrate having first and second surfaces, the silicon substrate including no oxide film or an oxide film having a thickness no greater than 100 nm, forming a first oxide film at least on ... | 10/25/2011 |
| 8034691 | HDP-CVD process, filling-in process utilizing HDP-CVD, and HDP-CVD system An HDP-CVD process is described, including a deposition step conducted in an HDP-CVD chamber and a pre-heating step that is performed outside of the HDP-CVD chamber before the deposition step and pre-heats a wafer to a temperature higher than room temperature and re... | 10/11/2011 |
| 7994013 | Semiconductor device and method of fabricating the semiconductor device A semiconductor device comprises a gate electrode on a semiconductor substrate, drift regions at opposite sides of the gate electrode, source and drain regions in the respective drift regions, and shallow trench isolation (STI) regions in the respective drift region... | 08/09/2011 |
| 7964467 | Method, structure and design structure for customizing history effects of soi circuits A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high-leakage dielectric formed between a gate electrode and an outer portion of an active region of a FET. Also provided is... | 06/21/2011 |
| 7935602 | Semiconductor processing methods The invention includes methods of forming isolation regions. An opening can be formed to extend into a semiconductor material, and an upper periphery of the opening can be protected with a liner while a lower periphery is unlined. The unlined portion can then be etc... | 05/03/2011 |
| 7892929 | Shallow trench isolation corner rounding A method for rounding the corners of a shallow trench isolation is provided. A preferred embodiment comprises filling the trench with a dielectric and recessing the dielectric to expose a portion of the sidewalls of the trench adjacent to the surface of the substrat... | 02/22/2011 |
| 7867862 | Semiconductor structure including high voltage device A high voltage device includes a substrate with a device region defined thereon. A gate stack is disposed on the substrate in the device region. A channel region is located in the substrate beneath the gate stack, while a first diffusion region is located in the sub... | 01/11/2011 |
| 7846801 | Method of fabricating semiconductor device Disclosed is a method of fabricating a semiconductor device including a multi-gate transistor. The method of fabricating a semiconductor device includes providing a semiconductor device having a number of active patterns which extend in a first direction, are separa... | 12/07/2010 |
| 7842577 | Two-step STI formation process A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming a first isolation region in the semiconductor substrate; after the step of forming the first isolation region, forming a metal-oxide-semiconductor (MOS) device ... | 11/30/2010 |
| 7838370 | Highly selective liners for semiconductor fabrication A method for manufacturing an isolation structure is disclosed that protects the isolation structure during etching of a dichlorosilane (DCS) nitride layer. The method involves the formation of a bis-(t-butylamino)silane-based nitride liner layer within the isolatio... | 11/23/2010 |
| 7811893 | Shallow trench isolation stress adjuster for MOS transistor The present invention provides, in one embodiment, a method of manufacturing a metal oxide semiconductor (MOS) transistor (100). The method comprises forming an active area (105) in a substrate (115), wherein the active area (105) is boun... | 10/12/2010 |
| 7795099 | Semiconductor devices having Fin-type active areas and methods of manufacturing the same A semiconductor device having a fin type active area includes a plurality of active regions, a first device isolation layer and a recessed second device isolation layer disposed in a direction of gate electrodes of the semiconductor device. A recessed second device ... | 09/14/2010 |
| 7781293 | Semiconductor device and method of fabricating the same including trenches of different aspect ratios A method of fabricating a semiconductor device includes etching a silicon oxide film, a silicon nitride film, a polycrystalline silicone film, and a gate insulating film in a predetermined pattern including a first opening width corresponding to a first trench and a... | 08/24/2010 |
| 7759204 | Process for high voltage superjunction termination A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termin... | 07/20/2010 |
| 7732287 | Method of forming a body-tie A method of forming a body-tie. The method includes forming the body-tie during an STI scheme of an SOI process. During the STI scheme, a first trench is formed. The first trench stops before a buried oxide layer of the SOI substrate. The first trench may determine ... | 06/08/2010 |
| 7713827 | Method for manufacturing semiconductor device Disclosed herein is a method of making a semiconductor device. According to the method, a flowable oxide (FOX) is deposited over a semiconductor substrate, and a local active region is exposed to grow an active region, by a silicon epitaxial growth (SEG) method, to ... | 05/11/2010 |
| 7700448 | Manufacturing method of semiconductor device The performance of the semiconductor device which formed the metal silicide layer in the salicide process is improved. An element isolation region is formed in a semiconductor substrate by the STI method, a gate insulating film is formed, a gate electrode is formed,... | 04/20/2010 |
| 7659170 | Method of increasing transistor drive current by recessing an isolation trench By recessing the isolation structure of a transistor prior to silicidation, the series resistance may be reduced due to the increased amount of metal silicide formed in the vicinity of the isolation structure. By recessing the isolation structure prior to the format... | 02/09/2010 |
| 7655524 | Method for manufacturing isolation layer having barrier layer formed thereon Embodiments relate to a semiconductor device and a method for manufacturing a semiconductor device. In embodiments, a transistor including the gate electrode and a source/drain may be formed between isolation layers and a contact may be connected to the source/drain... | 02/02/2010 |
| 7611950 | Method for forming shallow trench isolation in semiconductor device A method for forming shallow trench isolation in a semiconductor device. The method includes forming a pad oxide and a pad nitride on a semiconductor substrate in successive order, forming a trench in the substrate by etching the pad nitride, the pad oxide and the s... | 11/03/2009 |
| 7563683 | Transistor and method of fabricating the same Disclosed is a method for fabricating a gate of a field effect transistor. The method comprises a) forming a field oxide layer on a silicon substrate and then applying a photoresist layer in order to define a gate, b) etching the silicon substrate using the photores... | 07/21/2009 |
| 7547605 | Microelectronic device and a method for its manufacture Provided are a microelectronic device and a method for its manufacture. In one example, the method includes providing a semiconductor substrate layer having a first material (e.g., silicon or silicon germanium). An insulating layer is formed on the semiconductor sub... | 06/16/2009 |
| 7538002 | Semiconductor process integrating source/drain stressors and interlevel dielectric layer stressors A semiconductor fabrication process includes forming isolation structures on either side of a transistor region, forming a gate structure overlying the transistor region, removing source/drain regions to form source/drain recesses, removing portions of the isolation... | 05/26/2009 |
| 7531415 | Multilayered CMP stop for flat planarization A three layer film (116/114/112), such as nitride/oxide/nitride for a CMP stop layer (110). A gap filling material (120) is polished, stopping on the first film (112). The first film (112) is then stripped using an etch chemistry t... | 05/12/2009 |
| 7528046 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device including a substrate, a memory cell region including first pattern, first guard ring around the memory cell, second guard ring around the first guard ring, an isolation region between the first and second guard ring... | 05/05/2009 |
| 7528045 | MOS transistor and manufacturing methods thereof A method for manufacturing a metal-oxide semiconductor (MOS) transistor includes providing a substrate having at least a gate structure and a shallow trench isolation (STI) formed thereon, performing a first etching process to form recesses in the substrate respecti... | 05/05/2009 |
| 7524729 | Method of manufacturing a semiconductor integrated circuit device having a trench A semiconductor integrated circuit device and a method of manufacturing the same. The surface of a substrate of an active region surrounded by an element isolation trench is horizontally flat in the center portion of the active region but falls toward the side wall ... | 04/28/2009 |
| 7501326 | Method for forming isolation layer of semiconductor device A method for forming an isolation layer of a semiconductor device using a shallow trench isolation method is provided. The method includes: vertically etching a region of an insulating layer and a part of a semiconductor substrate corresponding thereto to form a tre... | 03/10/2009 |
| 7494883 | Semiconductor device having a trench isolation and method of fabricating the same The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to h... | 02/24/2009 |
| 7491614 | Methods for forming channel stop for deep trench isolation prior to deep trench etch Methods of manufacturing a semiconductor structure are disclosed including a deep trench isolation in which a channel stop is formed in the form of an embedded impurity region in the substrate prior to the deep trench etch and formation of transistor devices (FEOL p... | 02/17/2009 |
| 7488659 | Structure and methods for stress concentrating spacer A stress-concentrating spacer structure is a stack of an upper gate spacer with a low Young's modulus and a lower gate spacer with a high Young's modulus. The stacked spacer structure surrounds the gate electrode. The stress-concentrating spacer structure may contac... | 02/10/2009 |
| 7488658 | Stressed semiconductor device structures having granular semiconductor material A method of fabricating a semiconductor device structure, includes: providing a substrate, providing an electrode on the substrate, forming a recess in the electrode, the recess having an opening, disposing a small grain semiconductor material within the recess, cov... | 02/10/2009 |
| 7468302 | Method of forming trench type isolation film of semiconductor device A method of forming a trench type isolation film of a semiconductor device, including the steps of sequentially forming a pad oxide film and a nitride film for a hard mask on a semiconductor substrate in which a cell region and a peri region are defined; patterning ... | 12/23/2008 |
| 7456067 | Method with high gapfill capability for semiconductor devices A method of performing an STI gapfill process for semiconductor devices is provided. In a specific embodiment of the invention, the method includes forming an stop layer overlying a substrate. In addition, the method includes forming a trench within the substrate, w... | 11/25/2008 |
