Did You Know...
...that when IBM conducted a market study of Chester Carlson's invention in 1959, the company concluded that it would take only 5000 units of his new product to saturate the market? IBM therefore declined to be part of the new product introduction. Too bad for IBM. Carlson's invention was the xerography process, and his new product was the beginning of the Xerox Corporation. It is estimated that every day, worldwide, 3,000,000,000 copies are made!!
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| Number | Title | Issue Date |
| 8119489 | Method of forming a shallow trench isolation structure having a polysilicon capping layer A method of fabricating an isolation structure and the structure thereof is provided. The method is compatible with the embedded memory process and provides the isolation structure with a poly cap thereon to protect the top corners of the isolation structure, withou... | 02/21/2012 |
| 7902029 | Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor Processes for forming self-aligned, deposited source/drain, insulated gate, transistors and, in particular, FETs. By depositing a source/drain in a recess such that it remains only in the recess, the source/drain can be formed self-aligned to a gate and/or a channel... | 03/08/2011 |
| 7863144 | Semiconductor device and method for manufacturing the device Embodiments relate to a semiconductor device and a method for manufacturing the device, which suppresses off-current by improving the problem of leakage current due to hump characteristics, making it possible to maximize the reliability of the device. Embodiments re... | 01/04/2011 |
| 7452779 | Semiconductor devices having improved gate insulating layers and related methods of fabricating such devices Semiconductor devices are provided on a substrate having a cell array region and a peripheral circuit region. A first device isolation layer defines a cell active region in the cell array region and a second device isolation layer having first and second sidewalls d... | 11/18/2008 |
| 7440255 | Capacitor constructions and methods of forming A capacitor construction includes a first electrode and a layer between the first electrode and a surface supporting the capacitor construction. The capacitor construction can exhibit a lower RC time constant compared to an otherwise identical capacitor construction... | 10/21/2008 |
| 7384836 | Integrated circuit transistor insulating region fabrication method A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate electrode of the transistor. A recess is formed in the first doped wel... | 06/10/2008 |
| 7381616 | Method of making three dimensional, 2R memory having a 4F2 cell size RRAM A method of fabricating a multi-level 3D memory array includes: preparing a wafer and peripheral circuits thereon; layers of metal, memory resistor material, and metal are deposited, patterned and etched. The steps of the method of the invention are repeated for N l... | 06/03/2008 |
| 7374974 | Thyristor-based device with trench dielectric material A thyristor-based semiconductor device includes a thyristor body that has at least one region in the substrate and a thyristor control port in a trenched region of the device substrate. According to an example embodiment of the present invention, the trench is at le... | 05/20/2008 |
| 7368790 | Strained Si/SiGe/SOI islands and processes of making same A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under the active area to partially vertically isolate the active area. A the... | 05/06/2008 |
| 7364953 | Manufacturing method to construct semiconductor-on-insulator with conductor layer sandwiched between buried dielectric layer and semiconductor layers A method for treating exposed metal in a semiconductor wafer (301) in wafer processing is disclosed herein. In accordance with the method, a wafer is provided which is equipped with a metal layer (307) and a substrate (303), wherein a portion of... | 04/29/2008 |
| 7358161 | Methods of forming transistor devices associated with semiconductor-on-insulator constructions The invention encompasses a method of forming a semiconductor on-insulator construction. A substrate is provided. The substrate includes a semiconductor-containing layer over an insulative mass. The insulative mass comprises silicon dioxide. A band of material is fo... | 04/15/2008 |
| 7354812 | Multiple-depth STI trenches in integrated circuit fabrication Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider tre... | 04/08/2008 |
| 7342276 | Method and apparatus utilizing monocrystalline insulator A semiconductor device, including: a semiconductor material; a conductive element; and a substantially monocrystalline insulator disposed between the semiconductor material and the conductive eleme... | 03/11/2008 |
| 7341913 | Method of manufacturing non-volatile memory The invention is directed to a method for manufacturing a non-volatile memory. The method comprises steps of forming a mask layer on a substrate. An isolation structure is formed in the mask layer and the substrate, wherein the top surface of the isolation structure... | 03/11/2008 |
| 7339219 | Capacitance device including a perovskite film having (001) orientation A capacitance device including a substrate having a (111) orientation, an epitaxial film formed on the substrate and having a perovskite structure and a (001) orientation, and an electrode formed on the epitaxial film. The present invention may comprise devices havi... | 03/04/2008 |
| 7332399 | Method for manufacturing a semiconductor substrate and method for manufacturing a semiconductor in which film thicknesses can be accurately controlled A method of manufacturing semiconductor substrates. After supporting layers are provided on side walls of grooves formed in a semiconductor substrate, grooves that expose a second semiconductor layer are formed. Etching gas or etching liquid is brought in contact wi... | 02/19/2008 |
| 7320925 | SOI substrate, semiconductor substrate, and method for production thereof A method is for commercially producing by the SIMOX technique a perfect partial SOI structure avoiding exposure of a buried oxide film through the surface thereof and forming no step between an SOI region and a non-SOI region. A method for the production of a... | 01/22/2008 |
| 7306998 | Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect A method of forming an abrupt junction device with a semiconductor substrate is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed on the gate dielectric. A sidewall spacer is formed on the semiconductor substrate adjacent the g... | 12/11/2007 |
| 7300847 | MOS transistor on an SOI substrate with a body contact and a gate insulating film with variable thickness It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gat... | 11/27/2007 |
| 7300846 | Semiconductor device and method for manufacturing the same A semiconductor device and a method for manufacturing the same are disclosed, in which an insulating layer may be formed in a strained silicon layer under source/drain regions to substantially overcome conventional problems resulting from a channel decrease in the s... | 11/27/2007 |
| 7288819 | Stable PD-SOI devices and methods One aspect of the present subject matter relates to a partially depleted silicon-on-insulator structure. The structure includes a well region formed above an oxide insulation layer. In various embodiments, the well region is a multilayer epitaxy that includes a sili... | 10/30/2007 |
| 7279769 | Semiconductor device and manufacturing method thereof To suppress occurrence of dislocation in a substrate of a semiconductor device at an end portion of a gate electrode. Provided is a semiconductor device having a plurality of element formation regions formed over the main surface of a semiconductor substrate, an ele... | 10/09/2007 |
| 7268022 | Stable PD-SOI devices and methods One aspect of the present subject matter relates to a partially depleted silicon-on-insulator structure. The structure includes a well region formed above an oxide insulation layer. In various embodiments, the well region is a multilayer epitaxy that includes a sili... | 09/11/2007 |
| 7256980 | Thin film capacitors on ceramic Thin-film capacitors are formed on ceramic substrates having high capacitance densities and other desirable electrical and physical properties. The capacitor dielectrics are annealed at high temperatures. ... | 08/14/2007 |
| 7235459 | Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry. ... | 06/26/2007 |
| 7227228 | Silicon on insulator device and method of manufacturing the same An isolated semiconductor device and method for producing the isolated semiconductor device in which the device includes a silicon-on-insulator (SOI) device formed on a substrate. A dielectric film is formed on the insulator and covers the SOI device. The dielectric... | 06/05/2007 |
| 7217604 | Structure and method for thin box SOI device A method of forming a semiconductor device, including providing a substrate having a first insulative layer on a surface of the substrate, and a device layer on a surface of the first insulative layer, forming a spacer around the first insulative layer and the devic... | 05/15/2007 |
| 7199021 | Methods and systems to mitigate etch stop clipping for shallow trench isolation fabrication The present invention facilitates semiconductor fabrication by maintaining shape and density of an etch stop layer (206) during trench fill operations. The shape and density of the etch stop layer (206) is maintained by forming a protective alloy liner... | 04/03/2007 |
| 7189618 | Method of manufacturing a transistor of a semiconductor device Disclosed are a semiconductor device and a method of manufacturing the same. According to the present invention, the transistor of the semiconductor device comprises a stack type gate in which a tunnel oxide film, a floating gate, a dielectric film and a control gat... | 03/13/2007 |
| 7187032 | Integrated circuit devices having active regions with expanded effective widths An integrated circuit device includes a substrate that has a trench formed therein. An isolation layer is disposed in the trench and covers a first sidewall portion of the trench. A gate electrode is disposed on a second sidewall portion of the trench. ... | 03/06/2007 |
| 7176104 | Method for forming shallow trench isolation structure with deep oxide region The present invention relates to a shallow trench isolation structure and a method for forming a shallow trench isolation structure on a semiconductor substrate. A masking structure that includes a hard mask is formed over the semiconductor substrate and an etch is ... | 02/13/2007 |
| 7172914 | Method of making uniform oxide layer A method of forming a semiconductor structure includes forming an isolation region in a semiconductor substrate. A first oxide layer is on the substrate, a first sacrificial layer is on the first oxide layer, and a first nitride layer is on the first sacrificial lay... | 02/06/2007 |
| 7157762 | Semiconductor devices having improved gate insulating layers and related methods of fabricating such devices Semiconductor devices are provided on a substrate having a cell array region and a peripheral circuit region. A first device isolation layer defines a cell active region in the cell array region and a second device isolation layer having first and second sidewalls d... | 01/02/2007 |
| 7157385 | Method of depositing a silicon dioxide-comprising layer in the fabrication of integrated circuitry This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of depositing a silico... | 01/02/2007 |
| 7144790 | Shallow trench isolation type semiconductor device and method of forming the same A shallow trench isolation type semiconductor device is described, which includes a trench having a flexure in a bottom thereof. The flexure has a step difference of about 100 Å or more, and is preferably made at a middle area. Conventionally, a gate insulating la... | 12/05/2006 |
| 7129149 | Method for forming shallow trench isolation structure with anti-reflective liner The present invention relates to a shallow trench isolation structure and a method for forming a shallow trench isolation structure on a semiconductor substrate. A masking structure that includes a hard mask is formed over the semiconductor substrate, and an etch is... | 10/31/2006 |
| 7129138 | Methods of implementing and enhanced silicon-on-insulator (SOI) box structures Enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures and methods are provided for implementing enhanced SOI BOX structures. An oxygen implant step is performed from a backside into a thinned silicon substrate layer. An anneal step forms thick buried oxi... | 10/31/2006 |
| 7125815 | Methods of forming a phosphorous doped silicon dioxide comprising layer This invention includes methods of forming phosphorus doped silicon dioxide comprising layers, and methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of forming a phosphorus doped silicon dioxide comprisin... | 10/24/2006 |
| 7115463 | Patterning SOI with silicon mask to create box at different depths The present invention provides a method of fabricating a patterned silicon-on-insulator substrate which includes dual depth SOI regions or both SOI and non-SOI regions within the same substrate. The method of the present invention includes forming a silicon mask hav... | 10/03/2006 |
| 7112850 | Non-volatile memory device with a polarizable layer This invention concerns a non-volatile memory device with a polarizable layer. The apparatus concerns a substrate, a buried oxide layer within the substrate, and a polarizable layer within the substrate. The polarizable layer is formed in a buried oxide layer of a s... | 09/26/2006 |
