Class 438/294 - Including isolation structure

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process for making an insulated gate field effect transistor
No. of patents: 405
Last issue date: 04/10/2012

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Number	Title	Issue Date
8153493	FinFET process compatible native transistor Provided is a top-channel only finFET device. The methods and devices described herein may provide a native device that is compatible with a finFET process flow. A gate may be formed on the top of a fin providing the channel region of the device. In an embodiment, t...	04/10/2012
8138051	Integrated circuit system with high voltage transistor and method of manufacture thereof A method of manufacture of an integrated circuit system includes: providing a semiconductor substrate having an active region, implanted with impurities of a first type at a first concentration; forming an isolation region around the active region; forming a parasit...	03/20/2012
8114745	High voltage CMOS devices A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that...	02/14/2012
8097516	Dual trench isolation for CMOS with hybrid orientations The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present inv...	01/17/2012
7977198	Semiconductor device and method of manufacturing semiconductor device A semiconductor device is provided. The semiconductor device in which a field effect transistor utilizing a heterojunction is formed in a device formation region sectioned by a device separation region of a substrate comprising a semiconductor layer laminated while ...	07/12/2011
7875518	Semiconductor device having silicon layer in a gate electrode A method for forming a semiconductor device includes, in order, consecutively depositing a gate insulating film and a silicon layer on a semiconductor substrate, implanting boron into the silicon layer, diffusing the boron by heat-treating the silicon layer, implant...	01/25/2011
7833867	Semiconductor device and method for manufacturing the same A sacrifice oxide film is formed in a Fin semiconductor substrate portion, and impurities are then implanted in the semiconductor substrate through a mask pattern as a mask. Thereafter, the sacrifice oxide film is removed to expose the semiconductor substrate. A gat...	11/16/2010
7820516	Methods of manufacturing non-volatile memory devices having a vertical channel Disclosed are pairs of semiconductor flash memory cells including first and second source lines formed in a semiconductor substrate, semiconductor pillars extending from the substrate between the source lines, first and second charge storage structures formed on opp...	10/26/2010
7816216	Semiconductor device comprising transistor structures and methods for forming same A method for forming an opening within a semiconductor material comprises forming a neck portion, a rounded portion below the neck portion and, in some embodiments, a protruding portion below the rounded portion. This opening may be filled with a conductor, a dielec...	10/19/2010
7781292	High power device isolation and integration A structure and method of fabricating the structure. The structure including: a dielectric isolation in a semiconductor substrate, the dielectric isolation extending in a direction perpendicular to a top surface of the substrate into the substrate a first distance, ...	08/24/2010
7767533	Method and device for providing a contact structure An approach is provided for semiconductor devices and methods for providing a contact structure. Methods may include forming a gate pattern on a substrate including a device isolation pattern provided to define an active region, the gate pattern crossing over the ac...	08/03/2010
7759203	MOS transistor having protruded-shape channel and method of fabricating the same A MOS transistor that has a protruding portion with a favorable vertical profile and a protruded-shape channel that requires no additional photolithography process, and a method of fabricating the same are provided. A first mask that defines an isolation region of a...	07/20/2010
7727844	Gate structure of a semiconductor device Embodiments relate to a gate structure of a semiconductor device and a method of manufacturing the gate structure. An oxide layer may be formed on a silicon substrate before a gate insulating layer is formed. The oxide layer may be etched to form an opening exposing...	06/01/2010
7723194	Semiconductor device having silicide layers and method of fabricating the same Some embodiments include an isolation layer defining an active region of a substrate, a gate pattern formed on the active region, and source/drain regions formed in the active region. Sidewall spacers are formed on sidewalls of the gate pattern, and a blocking insul...	05/25/2010
7709335	Method of manufacturing semiconductor device including isolation process Provided may be a method of manufacturing a semiconductor device. The method may include forming a plurality of isolation patterns including conductive patterns on a semiconductor substrate and forming gaps between the isolation patterns, forming active patterns fil...	05/04/2010
7704842	Lateral high-voltage transistor with vertically-extended voltage-equalized drift region A lateral high-voltage device in which conductive trench plates are inserted across the voltage-withstand region, so that, in the on state, the current density vectors have less convergence. This can help reduce on-resistance. ...	04/27/2010
7687361	Method of fabricating a transistor having a triple channel in a memory device Disclosed is a method for fabricating a transistor of a memory device capable of preventing voids from being created when forming a low-resistant gate electrode. The method includes the steps of forming an active area by etching a semiconductor substrate, forming a ...	03/30/2010
7687362	Semiconductor device with increased channel length and width and method for manufacturing the same A semiconductor device includes a semiconductor substrate having an active region including a channel portion. An isolation layer is formed in the semiconductor substrate to define the active region, and a gate is formed over the channel portion in the active region...	03/30/2010
7662691	Method for fabricating semiconductor device with epitaxial growth A semiconductor device comprises an active region including a first active area to be a source/drain and a second active area to be a gate, and a device isolation region defining the active region. The first active area is obtained by growing a semiconductor substra...	02/16/2010
7662690	Method of preparing a semiconductor substrate utilizing plural implants under an isolation region to isolate adjacent wells Multiple blanket implantations of one or more p type dopants into a semiconductor substrate are performed to facilitate isolation between nwell regions subsequently formed in the substrate. The blanket implantations are performed through isolation regions in the sub...	02/16/2010
7541247	Guard ring structures for high voltage CMOS/low voltage CMOS technology using LDMOS (lateral double-diffused metal oxide semiconductor) device fabrication A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure. The semiconductor structure includes a semiconductor substrate. The method further includes simultaneously forming a first doped transistor region o...	06/02/2009
7468301	PMOS transistor with increased effective channel length in the peripheral region and a multi-height substrate In manufacturing a PMOS transistor, a semiconductor substrate having an active region and a field region is formed with a hard mask layer, which covers a center portion of the active region on the substrate in a lengthwise direction of a channel. The hard mask layer...	12/23/2008
7462544	Methods for fabricating transistors having trench gates A transistor including an active region and methods thereof. The active region may include corners with at least one of a rectangular, curved or rounded shape. The methods may include isotropically etching at least a portion of the active region such that the portio...	12/09/2008
7439131	Flash memory device having resistivity measurement pattern and method of forming the same A flash memory device has a resistivity measurement pattern and method of forming the same. A trench is formed in an isolation film in a Self-Aligned Floating Gate (SAFG) scheme. The trench is buried to form a resistivity measurement floating gate. This allows the r...	10/21/2008
7436030	Strained MOSFETs on separated silicon layers A method of fabricating and a structure of an IC incorporating strained MOSFETs on separated silicon layers are disclosed. N-channel field effect transistors (nFET) and P-channel FETs (pFET) are formed on the separated silicon layers, respectively. Shallow trench in...	10/14/2008
7432163	Method of manufacturing semiconductor device that includes forming adjacent field regions with a separating region therebetween A method of manufacturing a semiconductor device comprises the steps of: preparing a semiconductor substrate, the semiconductor substrate having first and second predetermined regions; forming a first field region surrounding the first predetermined region; forming ...	10/07/2008
7384836	Integrated circuit transistor insulating region fabrication method A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate electrode of the transistor. A recess is formed in the first doped wel...	06/10/2008
7374999	Semiconductor device A semiconductor device includes a substrate including a high-voltage transistor area provided with a high-voltage transistor and a low-voltage transistor area provided with a low-voltage transistor; a LOCOS layer provided as a device isolation layer of the high-volt...	05/20/2008
7364955	Methods of manufacturing semiconductor devices having single crystalline silicon layers Methods of manufacturing semiconductor devices having at least one single crystal silicon layer are provided. Pursuant to these methods, a first seed layer that includes silicon is formed. A first non-single crystalline silicon layer is then formed on the first seed...	04/29/2008
7361540	Method of reducing noise disturbing a signal in an electronic device Certain aspects of a method for reducing noise disturbing at least one signal in an electronic device may comprise shielding a first layer doped with a first dopant from a signaling layer employing a second layer doped with a second dopant. A first signaling compone...	04/22/2008
7358574	Semiconductor device having silicide-blocking layer and fabrication method thereof A semiconductor device having a silicide-blocking layer is provided. The device includes a field oxide layer defining an active region, source/drain regions in the active region of a substrate, a gate oxide layer and a gate electrode on the substrate between the sou...	04/15/2008
7348254	Method of fabricating fin field-effect transistors A method of fabricating a fin field-effect transistor that may enable a reduction in the number of process steps, by forming the fin structure by etching away a predetermined thickness of an element isolation layer. The method includes steps of sequentially forming ...	03/25/2008
7348638	Rotational shear stress for charge carrier mobility modification A semiconductor structure and its method of fabrication utilize a semiconductor substrate having an active region mesa surrounded by an isolation trench. A first isolation region having a first stress is located in the isolation trench. A second isolation region hav...	03/25/2008
7342276	Method and apparatus utilizing monocrystalline insulator A semiconductor device, including: a semiconductor material; a conductive element; and a substantially monocrystalline insulator disposed between the semiconductor material and the conductive eleme...	03/11/2008
7342266	Field effect transistors with dielectric source drain halo regions and reduced miller capacitance A field effect transistor (FET) device includes a gate conductor and gate dielectric formed over an active device area of a semiconductor substrate. A drain region is formed in the active device area of the semiconductor substrate, on one side of the gate conductor,...	03/11/2008
7338870	Methods of fabricating semiconductor devices Methods of recovering damage on a semiconductor device by performing a hydrogen annealing process are disclosed. An example disclosed method includes forming an STI structure on a semiconductor substrate; forming a gate electrode and spacers on the sidewalls of the ...	03/04/2008
7332387	MOSFET structure and method of fabricating the same A MOSFET structure and a method of forming it are described. The thickness of a portion of the gate dielectric layer of the MOSFET structure adjacent to the drain region is increased to form a bird's beak structure. The gate-to-drain overlap capacitance is reduced b...	02/19/2008
7332790	Semiconductor device having an active area partially isolated by a lateral cavity A process of making a partial silicon-on-insulator ledge is disclosed. A deep implantation region is created in a substrate. During a lateral cavity etch, the deep implantation region resists etching. The lateral cavity etch acts to partially isolate an active area ...	02/19/2008
7329556	High-sensitivity image sensor and fabrication method thereof A method of fabricating a high-sensitivity image sensor and the same are disclosed. The disclosed method comprises: etching predetermined regions of active silicon and a buried oxide layer of a SOI substrate by using a mask to expose an N-type silicon substrate; imp...	02/12/2008
7326983	Selective silicon-on-insulator isolation structure and method A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into ...	02/05/2008

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Class 438/294 - Including isolation structure