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| Number | Title | Issue Date |
| 7749849 | Methods of selectively oxidizing semiconductor structures, and structures resulting therefrom Methods for selectively oxidizing a semiconductor structure include generating a gas cluster ion beam comprising an oxidizing source gas, directing the gas cluster ion beam to a region of a substrate adjacent a conductive line and exposing the region to the gas clus... | 07/06/2010 |
| 7374974 | Thyristor-based device with trench dielectric material A thyristor-based semiconductor device includes a thyristor body that has at least one region in the substrate and a thyristor control port in a trenched region of the device substrate. According to an example embodiment of the present invention, the trench is at le... | 05/20/2008 |
| 7352631 | Methods for programming a floating body nonvolatile memory A technique to speed up the programming of a non-volatile memory device that has a floating body actively removes holes from the floating body that have accumulated after performing hot carrier injection (HCI). The steps of HCI and active hole removal can be alterna... | 04/01/2008 |
| 7344947 | Methods of performance improvement of HVMOS devices Methods fabricate DEMOS devices having varied channel lengths and substantially similar threshold voltages. A threshold voltage is selected for first and second devices. First and second well regions are formed. First and second drain extension regions are formed wi... | 03/18/2008 |
| 7342276 | Method and apparatus utilizing monocrystalline insulator A semiconductor device, including: a semiconductor material; a conductive element; and a substantially monocrystalline insulator disposed between the semiconductor material and the conductive eleme... | 03/11/2008 |
| 7335526 | Sensing system A ChemFET Sensing system is Described. ... | 02/26/2008 |
| 7332421 | Method of fabricating gate electrode of semiconductor device A method of forming a gate electrode of a semiconductor device includes forming a damascene pattern for fabricating a metal electrode on an upper part of a poly silicon gate so as to prevent a metal electrode from being oxidized when the poly silicon electrode and t... | 02/19/2008 |
| 7332433 | Methods of modulating the work functions of film layers Methods for fabricating two metal gate stacks with varying work functions for complementary metal oxide semiconductor (CMOS) devices are provided A first metal layer may be deposited onto a gate dielectric, followed by the deposition of a second metal layer, where t... | 02/19/2008 |
| 7265011 | Method of manufacturing a transistor A method of manufacturing a transistor according to some embodiments includes sequentially forming a dummy gate oxide layer and a dummy gate electrode on an active region of a semiconductor substrate, ion-implanting a first conductive impurity into source/drain regi... | 09/04/2007 |
| 7241920 | Filterable surfactant composition An improved aqueous soluble surfactant which has particular utility for incorporating in etchants for semiconductor devices is provided. The surfactant comprises a combination of a linear perfluorocarboxylic acid, a cyclic amine and an aliphatic alcohol. ... | 07/10/2007 |
| 7112289 | Etchants containing filterable surfactant An improved etching and cleaning composition for semiconductor devices is provided in which the etch solution incorporates a novel surfactant comprising a combination of a linear perfluorocarboxylic acid, a cyclic amine and an aliphatic alcohol. ... | 09/26/2006 |
| 7091078 | Selection of optimal quantization direction for given transport direction in a semiconductor device A technique for selecting an optimal quantization direction for a given transport direction in a semiconductor device such as a field effect transistor (FET), a method for preparing a wafer for fabricating such a semiconductor device, and the semiconductor device fa... | 08/15/2006 |
| 7091096 | Method of fabricating carbon nanotube field-effect transistors through controlled electrochemical modification The invention relates to a method of fabricating a structure with field-effect transistors each comprising a source electrode, a drain electrode, a channel extending between the source and drain electrodes and at least one gate electrode associated with the channel ... | 08/15/2006 |
| 7081391 | Integrated circuit devices having buried insulation layers and methods of forming the same An integrated circuit device includes a gate electrode formed on an active region of an integrated circuit device and on a field isolation layer adjacent to the active region. A source region and a drain region are in the active region on alternate sides of the gate... | 07/25/2006 |
| 7056795 | Thin-film transistor used as heating element for microreaction chamber The thin film transistor formed of polycrystalline silicon is positioned adjacent a heat reaction chamber. The gate electrode for the transistor is formed within a silicon substrate and a gate dielectric is positioned over the gate electrode. A pass transistor is co... | 06/06/2006 |
| 7030410 | Resistance variable device A method of precluding diffusion of a metal into adjacent chalcogenide material upon exposure to a quanta of actinic energy capable of causing diffusion of the metal into the chalcogenide material includes forming an actinic energy blocking material layer over the m... | 04/18/2006 |
| 6969662 | Semiconductor device A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate 13. Each of the data storage cells includes a field effect transistor having a source 18, drain 22 and gat... | 11/29/2005 |
| 6913961 | Method of manufacturing high-k gate dielectric by use of annealing in high-pressure hydrogen atmosphere Disclosed is a method of manufacturing a high-k gate dielectric, characterized in that an annealing process in a forming gas atmosphere, corresponding to a final step of a manufacturing process of a semiconductor device based on MOSFET fabrication techniques, is app... | 07/05/2005 |
| 6833559 | Non-volatile resistance variable device A method of precluding diffusion of a metal into adjacent chalcogenide material upon exposure to a quanta of actinic energy capable of causing diffusion of the metal into the chalcogenide material includes forming an actinic energy blocking material layer over the m... | 12/21/2004 |
| 6680227 | Non-volatile memory device and fabrication method thereof A nonvolatile read-only memory device, wherein a word line is on a substrate and the word line includes a metal layer a polysilicon line. A trapping layer is further located between the word line and the substrate. A polysilicon protection line is formed ... | 01/20/2004 |
| 6680503 | Field-effect transistor structure with an insulated gate The field-effect transistor has an insulated gate, a source electrode, a drain electrode, and an inversion channel between the source and drain electrodes and underneath the gate electrode. The gate electrode is fabricated from a material which does not h... | 01/20/2004 |
| 6620694 | Method of making non volatile memory with a protective metal line A non-volatile memory and the fabrication thereof are described. The non-volatile memory comprises a word-line on a substrate, a charge trapping layer between the word-line and the substrate, and a contact electrically connecting with the word-line over t... | 09/16/2003 |
| 6514827 | Method for fabricating a dual metal gate for a semiconductor device A method for fabricating a dual metal gate structure for a semiconductor device including deposition of a semiconductor substrate having PMOS and NMOS regions, a first gate having a first insulating layer and a first metal layer is formed in a first regio... | 02/04/2003 |
| 6475879 | Semiconductor wafer, method for processing the same and method for manufacturing semiconductor device A method is provided for processing a semiconductor wafer having a chip region where chips are formed and a non-chip region where chips are not normally formed. The method includes the steps of forming trench isolation regions in the semiconductor wafer, ... | 11/05/2002 |
| 6417053 | Fabrication method for a silicon nitride read-only memory A fabrication method for a silicon nitride read-only memory is described. A silicon nitride read-only memory and a grounding doped region are formed in the substrate. A contact is formed on the substrate. A metal protection line is also formed, wherein th... | 07/09/2002 |
| 6306692 | Coplanar type polysilicon thin film transistor and method of manufacturing the same The present invention discloses a method of manufacturing a thin film transistor, including: depositing an amorphous silicon layer, an insulating layer, and a gate metal layer on a substrate sequentially; patterning the insulating layer and the gate metal... | 10/23/2001 |
| 6143586 | Electrostatic protected substrate An electrostatic protected integrated circuit (IC) substrate and a method of making an integrated circuit package with the electrostatic protected IC substrate includes an IC substrate, having a plurality of electrical traces formed on the top of the IC s... | 11/07/2000 |
| 5833749 | Compound semiconductor substrate and process of producing same A compound semiconductor substrate having at least one compound semiconductor layer epitaxially grown on a silicon single crystal substrate, wherein the silicon single crystal substrate has a surface on which the compound semiconductor layer is epitaxiall... | 11/10/1998 |
| 5798534 | Manufacture of electronic devices comprising thin-film circuitry In the manufacture of liquid-crystal display devices and other large-area electronics devices, electrostatic discharge damage (ESD) of tracks and other thin-film circuit elements can result during ion implantation and/or during handling. This damage is av... | 08/25/1998 |
| 5759898 | Production of substrate for tensilely strained semiconductor A process and method for producing strained and defect free semiconductor layers. In a preferred embodiment, silicon on insulator may be used as a substrate for the growth of fully relaxed SiGe buffer layers. A new strain relief mechanism operates, whereb... | 06/02/1998 |
| 5643816 | High-density programmable read-only memory and the process for its fabrication A read-only memory device having a memory array composed of memory cells formed as P-N junction diodes when programmed to be in an ON state and as blocking capacitors when remaining in an OFF state. A number of insulators are placed on the surface of a P-... | 07/01/1997 |
| 5543344 | Method of making programmable read-only memory A programmable read-only memory (PROM) and a method of fabrication are described. A plurality of bit-lines of a first conductivity type are formed in a semiconductor substrate and are spaced apart along a first direction. A dielectric layer is disposed on... | 08/06/1996 |
| 5391502 | Per-wafer method for globally stressing gate oxide during device fabrication Gate oxide on a semiconductor wafer is effectively stressed on a per-wafer basis during fabrication. Because it was effectively stressed, gross testing the gate oxide after device fabrication provides a good indication whether a completed MOS device will ... | 02/21/1995 |
| 5273927 | Method of making a ferroelectric capacitor and forming local interconnect Problems arise when connecting the bottom plate of a ferroelectric capacitor to the source of its associated access transistor during the fabrication of an ultra large scale integrated memory circuit. The temperature and ambient of certain steps of the fa... | 12/28/1993 |
| 5262350 | Forming a non single crystal semiconductor layer by using an electric current A semiconductor device which has a non-single crystal semiconductor layer formed on a substrate and in which the non-single crystal semiconductor layer is composed of a first semiconductor region formed primarily of non-single crystal semiconductor and a ... | 11/16/1993 |
| 5219773 | Method of making reoxidized nitrided oxide MOSFETs A method of fabricating a field-effect device having a gate dielectric of reoxidized nitrided oxide (RNO) provides an inversion layer mobility much higher than that of conventional RNO devices. A conductivity structure such as a metal oxide semiconductor ... | 06/15/1993 |
| 5208177 | Local field enhancement for better programmability of antifuse PROM The present invention provides improved programmability of antifuse elements by utilizing local enhancement of an underlying diffusion region. During an existing fabrication of a semiconductor device using antifuse elements after the access lines (usually... | 05/04/1993 |
| 4874711 | Method for altering characteristics of active semiconductor devices Method for altering an electrical characteristic of a circuit having at least one active semiconductor device involves applying at least one pulse--a voltage pulse, a current pulse, an energy pulse, or a power pulse and so forth--across the active semicon... | 10/17/1989 |
| 4562639 | Process for making avalanche fuse element with isolated emitter A programmable device is provided by a thin-oxide avalanche fuse element which is programmed at a voltage below the oxide breakdown level. This device may be used to fix the addresses of faulty rows or columns in a memory having redundant or substitute ce... | 01/07/1986 |
| 4502208 | Method of making high density VMOS electrically-programmable ROM A method of making an electrically-programmable memory array in which the memory elements are capacitor devices formed in anisotropically etched V-grooves, providing enhanced dielectric breakdown at the apex of the groove. After breakdown, a memory elemen... | 03/05/1985 |
