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| Number | Title | Issue Date |
| 8067289 | Semiconductor device and manufacturing method thereof A semiconductor device and a method of manufacturing a semiconductor device. A semiconductor device may include an epitaxial layer over a semiconductor substrate, a first well region over a epitaxial layer, a first isolation layer and/or a third isolation layer at o... | 11/29/2011 |
| 7501325 | Method for fabricating semiconductor device The method for fabricating the semiconductor device comprises: the step of forming a ferroelectric capacitor over a semiconductor substrate 10; the step of forming an insulating film 54, covering the ferroelectric capacitor; the step of processing ther... | 03/10/2009 |
| 7427546 | Transistor device and method for manufacturing the same A transistor device includes a recess in a surface of semiconductor substrate, a gate insulation layer formed over an inner side of the recess, a gate conductor filling the recess in which the gate insulation layer is formed, and source and drain regions located ove... | 09/23/2008 |
| 7393767 | Method for implanting a cell channel ion of semiconductor device A method for implanting a cell channel ion of semiconductor device is disclosed. In accordance with the method, the bit line contact region and the edge portion of the channel region adjacent to the bit line contact region in the cell region are subjected to a selec... | 07/01/2008 |
| 7381621 | Methods of fabricating high voltage MOSFET having doped buried layer A MOSFET includes an insulated gate electrode on a surface of a semiconductor substrate having an impurity region of first conductivity type therein that extends to the surface. Source and drain regions of second conductivity type are provided in the impurity region... | 06/03/2008 |
| 7371648 | Method for manufacturing a transistor device having an improved breakdown voltage and a method for manufacturing an integrated circuit using the same The present invention provides a method for manufacturing a transistor device, and a method for manufacturing an integrated circuit including the same. The method for manufacturing the transistor device, among other elements, includes forming a gate structure over a... | 05/13/2008 |
| 7364966 | Method for forming a buried digit line with self aligning spacing layer and contact plugs during the formation of a semiconductor device, semiconductor devices, and systems including same A method for use during fabrication of a semiconductor device comprises the formation of buried digit lines and contacts. During formation, a buried bit line layer may be used as a mask to etch one or more openings in a dielectric layer. A conductive layer is then f... | 04/29/2008 |
| 7354817 | Semiconductor device, manufacturing method thereof, and CMOS integrated circuit device A semiconductor device includes a semiconductor substrate. A gate electrode is formed on the semiconductor substrate via a gate insulating film. A source region and a drain region of a first conductivity type are formed on the first side and the second side of the g... | 04/08/2008 |
| 7354833 | Method for improving threshold voltage stability of a MOS device This invention provides a method for improving threshold voltage stability of at least one metal-oxide-semiconductor (MOS) device. In one embodiment of the invention, at least one well is formed on a semiconductor substrate. A gate dielectric layer is formed on the ... | 04/08/2008 |
| 7348243 | Semiconductor device and method for fabricating the same A transistor and a method for fabricating the same is disclosed, to uniformly provide impurity ions in impurity areas, and to prevent a short channel effect, in which the method for fabricating the transistor includes steps of forming a plurality of channel ion impl... | 03/25/2008 |
| 7344947 | Methods of performance improvement of HVMOS devices Methods fabricate DEMOS devices having varied channel lengths and substantially similar threshold voltages. A threshold voltage is selected for first and second devices. First and second well regions are formed. First and second drain extension regions are formed wi... | 03/18/2008 |
| 7342276 | Method and apparatus utilizing monocrystalline insulator A semiconductor device, including: a semiconductor material; a conductive element; and a substantially monocrystalline insulator disposed between the semiconductor material and the conductive eleme... | 03/11/2008 |
| 7335518 | Method for manufacturing semiconductor device In a manufacturing method for a semiconductor device, a main body wafer is formed, and a monitor wafer on which a monitor element is formed is provided. Characteristics of the main body wafer are copied onto the monitor element by simultaneously processing the main ... | 02/26/2008 |
| 7332421 | Method of fabricating gate electrode of semiconductor device A method of forming a gate electrode of a semiconductor device includes forming a damascene pattern for fabricating a metal electrode on an upper part of a poly silicon gate so as to prevent a metal electrode from being oxidized when the poly silicon electrode and t... | 02/19/2008 |
| 7326293 | Patterned atomic layer epitaxy A patterned layer is formed by removing nanoscale passivating particle from a first plurality of nanoscale structural particles or by adding nanoscale passivating particles to the first plurality of nanoscale structural particles. Each of a second plurality of nanos... | 02/05/2008 |
| 7323386 | Method of fabricating semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics A semiconductor device includes a field shield region that is doped opposite to the conductivity of the substrate and is bounded laterally by dielectric sidewall spacers and from below by a PN junction. For example, in a trench-gated MOSFET the field shield region m... | 01/29/2008 |
| 7323377 | Increasing self-aligned contact areas in integrated circuits using a disposable spacer In one embodiment, a method of fabricating an integrated circuit includes the steps of: (i) forming composite spacers on sidewalls of a transistor gate, each of the composite spacers comprising a first liner having a stepped portion and a disposable spacer material ... | 01/29/2008 |
| 7320919 | Method for fabricating semiconductor device with metal-polycide gate and recessed channel A method for fabricating a semiconductor device with a metal-polycide gate and a recessed channel, including the steps of: forming trenches for a recessed channel in an active area of a semiconductor substrate; forming a gate insulating layer on the semiconductor su... | 01/22/2008 |
| 7312125 | Fully depleted strained semiconductor on insulator transistor and method of making the same An integrated circuit includes multiple layers. A semiconductor-on-insulator (SOI) wafer can be used to house transistors. Two substrates or wafers can be bonded to form the multiple layers. A strained semiconductor layer can be between a silicon germanium layer and... | 12/25/2007 |
| 7288445 | Double gated transistor and method of fabrication Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric... | 10/30/2007 |
| 7285823 | Superjunction semiconductor device structure In one embodiment, a charge compensation region is formed in a body of semiconductor material. A conductive layer is coupled to the charge compensation layer. In a further embodiment, the charge compensation region comprises a trench filled with opposite conductivit... | 10/23/2007 |
| 7282439 | Anti-reflective coating doped with carbon for use in integrated circuit technology and method of formation The invention pertains to films comprising silicon, oxygen and carbon and the use of the films in integrated circuit technology, such as capacitor constructions, DRAM constructions, semiconductive material assemblies, etching processes, and methods for forming capac... | 10/16/2007 |
| 7279388 | Method for manufacturing transistor in semiconductor device Disclosed is a method for manufacturing a transistor in a semiconductor device, which can improve a device's refresh characteristics. The method includes: providing a silicon substrate having active and field regions; performing a channel ion implantation into the s... | 10/09/2007 |
| 7279725 | Vertical diode structures A method of making a vertical diode structure is provided, the vertical diode structure having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interio... | 10/09/2007 |
| 7274076 | Threshold voltage adjustment for long channel transistors A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor includes a substrate with spaced-apart source and drain regions formed in the substrate and a channel regi... | 09/25/2007 |
| 7273788 | Ultra-thin semiconductors bonded on glass substrates A method for forming a semiconductor on insulator structure includes providing a glass substrate, providing a semiconductor wafer, and performing a bonding cut process on the semiconductor wafer and the glass substrate to provide a thin semiconductor layer bonded to... | 09/25/2007 |
| 7271078 | Method for fabricating semiconductor device and semiconductor device using the same A method for fabricating a semiconductor device improves off-state leakage current and junction capacitance characteristics in a pMOS transistor. The method includes forming a device isolation layer defining an active area in a semiconductor substrate; and forming a... | 09/18/2007 |
| 7268065 | Methods of manufacturing metal-silicide features A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the se... | 09/11/2007 |
| 7265405 | Method for fabricating contacts for integrated circuits, and semiconductor component having such contacts One (or more) contacts are produced on one or more active areas of a semiconductor wafer, it being possible for one or more isolated control lines to be arranged on the active areas with which contact is to be made. The control lines may, for example, be gate lines.... | 09/04/2007 |
| 7262428 | Strained Si/SiGe/SOI islands and processes of making same A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under the active area to partially vertically isolate the active area. A the... | 08/28/2007 |
| 7261777 | Method for fabricating an epitaxial substrate A method for fabricating an epitaxial substrate. The technique includes providing a crystalline or mono-crystalline base substrate, implanting atomic species into a front face of the base substrate to a controlled mean implantation depth to form a zone of weakness w... | 08/28/2007 |
| 7259054 | Method of manufacturing a semiconductor device that includes a process for forming a high breakdown voltage field effect transistor With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, n+ type semiconductor regions, each having a conduction type opposite to p+ type s... | 08/21/2007 |
| 7256096 | Semiconductor device having a dual-damascene gate and manufacturing method thereof A method of manufacturing a semiconductor device having a dual-damascene gate including forming LDD regions by forming a gate oxide film on a semiconductor substrate, and by implanting lowly-concentrated impurities in the semiconductor substrate in accordance with a... | 08/14/2007 |
| 7253066 | MOSFET with decoupled halo before extension An inverse-T transistor is formed by a method that decouples the halo implant, the deep S/D implant and the extension implant, so that the threshold voltage can be set by adjusting the halo implant without being affected by changes to the extension implant that are ... | 08/07/2007 |
| 7247541 | Method of manufacturing a semiconductor memory device including a transistor A semiconductor device comprises a plurality of gate structures formed on a substrate, a gate spacer formed on a sidewall of the gate structures, a semiconductor pattern formed on the substrate between the gate structures, a first impurity region and a second impuri... | 07/24/2007 |
| 7242063 | Symmetric non-intrusive and covert technique to render a transistor permanently non-operable A technique for and structures for camouflaging an integrated circuit structure. The technique including forming active areas of a first conductivity type and LDD regions of a second conductivity type resulting in a transistor that is always non-operational when sta... | 07/10/2007 |
| 7241673 | Methods of forming silicon-doped aluminum oxide, and methods of forming transistors and memory devices The invention encompasses a method of forming a silicon-doped aluminum oxide. Aluminum oxide and silicon monoxide are co-evaporated. Subsequently, at least some of the evaporated aluminum oxide and silicon monoxide is deposited on a substrate to form the silicon-dop... | 07/10/2007 |
| 7238573 | Method for fabricating a trench transistor of semiconductor device A method for fabricating a semiconductor transistor including forming a first insulating layer on a semiconductor substrate; forming an LDD region using ion implantation; patterning the first insulating layer; forming a trench in the substrate; forming a trench gate... | 07/03/2007 |
| 7226803 | Photodiode with ultra-shallow junction for high quantum efficiency CMOS image sensor and method of formation A pinned photodiode with an ultra-shallow highly-doped surface layer of a first conductivity type and a method of formation are disclosed. The ultra-shallow highly-doped surface layer has a thickness of about 100 Angstroms to about 500 Angstroms and a dopant concent... | 06/05/2007 |
| 7226509 | Method for fabricating a carrier substrate A method for fabricating a carrier substrate. The technique includes providing a crystalline or mono-crystalline base substrate, growing a stiffening layer on a front face of the base substrate at a thickness sufficient to form a carrier substrate for subsequent pro... | 06/05/2007 |
