Did You Know...
...that Robert Adler has the dubious distinction of being the Father of the Couch Potato? Back in 1955 Adler was employed by what was then Zenith Radio Corp., where he was charged to invent something that would allow viewers to turn down the TV volume without leaving their chairs. After a series of flops (such as a wired contraption that people tripped over), Adler hit on the idea of using sound waves. Thus the Remote Control was born...
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| Number | Title | Issue Date |
| 8105907 | Manufacturing method of semiconductor memory device To provide a manufacturing method of a semiconductor memory device, the method including forming contact plugs to be connected to a drain region or a source region of each of transistors, by using a SAC line technique of selectively etching an insulation layer that ... | 01/31/2012 |
| 7977196 | Semiconductor device with increased channel area and fabrication method thereof A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around ... | 07/12/2011 |
| 7972930 | Transistor and method of manufacturing the same In a transistor and a method of manufacturing the same, the transistor includes a channel layer arranged on a substrate, a source electrode and a drain electrode formed on the substrate so as to contact respective ends of the channel layer, a gate insulating layer s... | 07/05/2011 |
| 7968409 | Mixed-signal semiconductor platform incorporating fully-depleted castellated-gate MOSFET device and method of manufacture thereof A Mixed-Signal Semiconductor Platform Incorporating Castellated-Gate MOSFET device(s) capable of Fully-Depleted operation is disclosed along with a method of making the same. The composite device/technology platform has robust I/O applications and includes a startin... | 06/28/2011 |
| 7964466 | FinFET transistor and circuit A drive strength tunable FinFET, a method of drive strength tuning a FinFET, a drive strength ratio tuned FinFET circuit and a method of drive strength tuning a FinFET, wherein the FinFET has either at least one perpendicular and at least one angled fin or has at le... | 06/21/2011 |
| 7955932 | Single electron transistor and method of manufacturing the same A single electron transistor includes source/drain layers disposed apart on a substrate, at least one nanowire channel connecting the source/drain layers, a plurality of oxide channel areas in the nanowire channel, the oxide channel areas insulating at least one por... | 06/07/2011 |
| 7939412 | Process for forming an electronic device including a fin-type transistor structure An electronic device can include an insulating layer and a fin-type transistor structure. The fin-type structure can have a semiconductor fin and a gate electrode spaced apart from each other. A dielectric layer and a spacer structure can lie between the semiconduct... | 05/10/2011 |
| 7799646 | Integration of a sense FET into a discrete power MOSFET A semiconductor device includes a main field effect transistor (FET) and one or more sense FETs, and a common gate pad. The main FET and the one or more sense FETs are formed in a common substrate. The main FET and each of the sense FETs include a source terminal, a... | 09/21/2010 |
| 7790555 | Semiconductor device manufacturing method with spin-coating of photoresist material A semiconductor device manufacturing method includes a field oxide insulation film forming step, an electrode forming step, and a resistor forming step. The field oxide insulation film forming step comprises forming a field oxide insulation film on a surface of the ... | 09/07/2010 |
| 7642167 | SON MOSFET using a beam structure and method for fabricating thereof The present invention relates to a SON (Silicon-On-Nothing) MOSFET having a beam structure and an inverter using thereof and the method for fabricating thereof to increase the efficiency and performance of a MOSFET. A method for fabricating the SON MOSFET according ... | 01/05/2010 |
| 7638398 | Semiconductor device with increased channel area and fabrication method thereof A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around ... | 12/29/2009 |
| 7560347 | Methods for forming a wrap-around gate field effect transistor A field effect transistor is formed having wrap-around, vertically-aligned, dual gate electrodes. Starting with a silicon-on-insulator (SOI) structure having a buried silicon island, a vertical reference edge is defined, by creating a cavity within the SOI structure... | 07/14/2009 |
| 7541245 | Semiconductor device with silicon-film fins and method of manufacturing the same A semiconductor device includes a semiconductor substrate, an insulating film projected on a surface of the semiconductor substrate, a semiconductor film provided on a side surface of the insulating film, and MIS transistor formed in the semiconductor film, the MIS ... | 06/02/2009 |
| 7514327 | Electronically scannable multiplexing device An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The d... | 04/07/2009 |
| 7439139 | Fully-depleted castellated gate MOSFET device and method of manufacture thereof A fully depleted castellated-gate MOSFET device is disclosed along with a method of making the same. The device has robust I/O applications, and includes a semiconductor substrate body having an upper portion with an upper end surface and a lower portion with a lowe... | 10/21/2008 |
| 7435653 | Methods for forming a wrap-around gate field effect transistor A field effect transistor is formed having wrap-around, vertically-aligned, dual gate electrodes. Starting with a silicon-on-insulator (SOI) structure having a buried silicon island, a vertical reference edge is defined, by creating a cavity within the SOI structure... | 10/14/2008 |
| 7427541 | Carbon nanotube energy well (CNEW) field effect transistor A structure to form an energy well within a Carbon nanotube is described. The structure includes a doped semiconductor region and an undoped semiconductor region. The Carbon nanotube is between the doped semiconductor region and the undoped semiconductor region. The... | 09/23/2008 |
| 7425487 | Method for fabricating a nanoelement field effect transistor with surrounded gate structure The invention relates to a method for the production of a nanoelement field effect transistor, a nanoelement field effect transistor and a nanoelement arrangement. According to the method for the production of a nanoelement field effect transistor, a nanoelement is ... | 09/16/2008 |
| 7413955 | Transistor for memory device and method for manufacturing the same Disclosed is a transistor for a memory device realizing both a step-gated asymmetry transistor and a fin transistor in a cell and a method for manufacturing the same. The transistor has an active region protruding from a predetermined region of a substrate and a gro... | 08/19/2008 |
| 7407845 | Field effect transistor and method for manufacturing the same In one embodiment, a semiconductor device includes a semiconductor substrate having a lower layer and an upper layer overlying the lower layer. The upper layer is arranged and structured to form first and second active regions that are spaced apart from each other a... | 08/05/2008 |
| 7393733 | Methods of forming hybrid fin field-effect transistor structures Semiconductor-on-insulator structures facilitate the fabrication of devices, including MOSFETs that are at least partially depleted during operation and FinFETs including bilayer fins and/or crystalline oxide. ... | 07/01/2008 |
| 7381601 | Methods of fabricating field effect transistors having multiple stacked channels Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at le... | 06/03/2008 |
| 7368355 | FinFET transistor and circuit A drive strength tunable FinFET, a method of drive strength tuning a FinFET, a drive strength ratio tuned FinFET circuit and a method of drive strength tuning a FinFET, wherein the FinFET has either at least one perpendicular and at least one angled fin or has at le... | 05/06/2008 |
| 7348246 | Methods of fabricating non-volatile memory devices including divided charge storage structures A semiconductor memory device includes a substrate having first and second source/drain regions therein and a channel region therebetween. The device also includes first and second charge storage layers on the channel region, a first insulating layer on the channel ... | 03/25/2008 |
| 7348225 | Structure and method of fabricating FINFET with buried channel A method of manufacturing a fin structure comprises forming a first structure of a first material type on a wafer and forming a buried channel of a second material adjacent sidewalls of the first structure. The second material type is different than the first materi... | 03/25/2008 |
| 7341916 | Self-aligned nanometer-level transistor defined without lithography A field effect transistor (FET) device structure and method for forming FETs for scaled semiconductor devices. Specifically, FinFET devices are fabricated from silicon-on-insulator (SOI) wafers in a highly uniform and reproducible manner. The method facilitates form... | 03/11/2008 |
| 7341915 | Method of making planar double gate silicon-on-insulator structures Methods are provided for forming a semiconductor device from a substrate comprising a bottom gate layer, a channel layer overlying the bottom gate layer, and a top gate structure formed over the channel layer. First, a hardmask comprising a first material interposed... | 03/11/2008 |
| 7326634 | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication A method of a bulk tri-gate transistor having stained enhanced mobility and its method of fabrication. The present invention is a nonplanar transistor having a strained enhanced mobility and its method of fabrication. The transistor has a semiconductor body formed o... | 02/05/2008 |
| 7274051 | Field effect transistor (FET) having wire channels and method of fabricating the same In a field effect transistor (FET), and a method of fabricating the same, the FET includes a semiconductor substrate, source and drain regions formed on the semiconductor substrate, a plurality of wire channels electrically connecting the source and drain regions, t... | 09/25/2007 |
| 7271448 | Multiple gate field effect transistor structure A multiple gate region FET device for forming up to 6 FET devices and method for forming the same, the device including a multiple fin shaped structure comprising a semiconductor material disposed on a substrate; said multiple fin shaped structure comprising substan... | 09/18/2007 |
| 7265426 | High-voltage MOS transistor and corresponding manufacturing method A high-voltage MOS transistor having: a first region of a first conductivity type; a source region of the second conductivity type, which is introduced into the first region; a drain region of the second conductivity type, which is introduced into the first region; ... | 09/04/2007 |
| 7259430 | Non-volatile memory device and method of manufacturing the same A non-volatile memory device includes a fin body protruded from a semiconductor substrate. The fin body has first and second side surfaces opposite to each other. An inner dielectric layer pattern is formed on an upper surface, and the first and second side surfaces... | 08/21/2007 |
| 7253060 | Gate-all-around type of semiconductor device and method of fabricating the same A gate-all-around (GAA) transistor device has a pair of pillars that include the source/drain regions, a channel region bridging the source/drain regions, and a gate electrode and gate oxide which surround the channel region. The pillars are formed by providing a mo... | 08/07/2007 |
| 7223657 | Methods of fabricating flash memory devices with floating gates that have reduced seams Methods of fabricating a floating gate of a flash memory cell are provided in which a first polysilicon layer is formed between first and second isolation layers. An upper region of the first polysilicon layer is then oxidized. The oxidized upper region of the first... | 05/29/2007 |
| 7187022 | Semiconductor device having a multi-bridge-channel and method for fabricating the same In a semiconductor device having a multi-bridge-channel, and a method for fabricating the same, the device includes first and second semiconductor posts protruding from a surface of a semiconductor substrate and having a source and a drain region, respectively, in u... | 03/06/2007 |
| 7187179 | Wiring test structures for determining open and short circuits in semiconductor devices A wiring test structure includes a plurality of wiring traces configured in an interleaving spiral pattern. At least one of the plurality of wiring traces configured for open circuit testing therein, and at least a pair of the plurality of wiring traces is configure... | 03/06/2007 |
| 7186592 | High performance, integrated, MOS-type semiconductor device and related manufacturing process An LDMOS device includes elementary MOS cells. The gate structure of the elementary cell includes a first conductor material finger. The LDMOS device includes first metal stripes for contacting source regions, second metal stripes for contacting drain regions, and t... | 03/06/2007 |
| 7179713 | Method of fabricating a fin transistor A method of fabricating a fin transistor is disclosed. An example method stacks a mask oxide layer and a nitride layer on a semiconductor substrate, forms a fin by etching the nitride and mask oxide layers and silicon, forms an insulating oxide layer, and forms a ga... | 02/20/2007 |
| 7169655 | Field effect transistors and methods for manufacturing field effect transistors FETs and methods for fabricating FETs are disclosed. An illustrated method comprises forming a first insulating layer on a semiconductor substrate; forming a first conductive layer for a fin on the first insulating layer; etching the first conductive layer so that a... | 01/30/2007 |
| 7160780 | Method of manufacturing a fin field effect transistor In an exemplary embodiment, a fin active region is protruded along one direction from a bulk silicon substrate on which a shallow trench insulator is entirely formed so as to cover the fin active region. The shallow trench insulator is removed to selectively expose ... | 01/09/2007 |
