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Combination Beverage Container and Spittoon
A combination beverage container and spittoon includes a bottom portion including outer wall and a first inner wall defining a spittoon space.
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| Number | Title | Issue Date |
| 8435852 | HBT with configurable emitter A heterojunction bipolar transistor is formed with an emitter electrode that comprises an emitter epitaxy underlying an emitter metal cap and that has horizontal dimensions that are substantially equal to the emitter metal cap. ... | 05/07/2013 |
| 8247287 | Method of fabricating a deep trench insulated gate bipolar transistor In one embodiment, a method comprises forming an epitaxial layer over a substrate of an opposite conductivity type, the epitaxial layer being separated by a buffer layer having a doping concentration that is substantially constant in a vertical direction down to the... | 08/21/2012 |
| 8143120 | Multiple doping level bipolar junctions transistors and method for forming A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A... | 03/27/2012 |
| 8058124 | Method of manufacturing a semiconductor device The semiconductor device, which provides reduced electric current leakage and parasitic resistance to achieve stable current gain, is provided. A first polycrystalline semiconductor layer is grown on a p-type polycrystalline silicon film exposed in a lower surface o... | 11/15/2011 |
| 8043910 | Integrated semiconductor structure including a heterojunction bipolar transistor and a Schottky diode An integrated semiconductor structure includes a heterojunction bipolar transistor and a Schottky diode. The structure has a substrate, the heterojunction bipolar transistor overlying and contacting the substrate, wherein the heterojunction bipolar transistor includ... | 10/25/2011 |
| 7998807 | Method for increasing the speed of a light emitting biopolar transistor device A method for increasing the speed of a bipolar transistor, includes the following steps: providing a bipolar transistor having emitter, base, and collector regions; providing electrodes for coupling electrical signals with the emitter, base, and collector regions; a... | 08/16/2011 |
| 7910425 | Multiple doping level bipolar junctions transistors and method for forming A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A... | 03/22/2011 |
| 7892915 | High performance SiGe:C HBT with phosphorous atomic layer doping A base structure for high performance Silicon Germanium:Carbon (SiGe:C) based heterojunction bipolar transistors (HBTs) with phosophorus atomic layer doping (ALD) is disclosed. The ALD process subjects the base substrate to nitrogen gas (in ambient temperature appro... | 02/22/2011 |
| 7888199 | PNP light emitting transistor and method A semiconductor light-emitting transistor device, including: a bipolar pnp transistor structure having a p-type collector, an n-type base, and a p-type emitter; a first tunnel junction coupled with the collector, and a second tunnel junction coupled with the emitter... | 02/15/2011 |
| 7871882 | Method of fabricating a deep trench insulated gate bipolar transistor In one embodiment, a method comprises forming an epitaxial layer over a substrate of an opposite conductivity type, the epitaxial layer being separated by a buffer layer having a doping concentration that is substantially constant in a vertical direction down to the... | 01/18/2011 |
| 7824978 | Bipolar transistor with high dynamic performances A bipolar transistor with very high dynamic performance, usable in an integrated circuit. The bipolar transistor has a single-crystal silicon emitter region with a thickness smaller than 50 nm. The base of the bipolar transistor is made of an SiGe alloy. ... | 11/02/2010 |
| 7718486 | Structures and methods for fabricating vertically integrated HBT-FET device Methods and systems for fabricating integrated pairs of HBT/FET's are disclosed. One preferred embodiment comprises a method of fabricating an integrated pair of GaAs-based HBT and FET. The method comprises the steps of: growing a first set of epitaxial layers for f... | 05/18/2010 |
| 7713811 | Multiple doping level bipolar junctions transistors and method for forming A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A... | 05/11/2010 |
| 7704824 | Semiconductor layer The present invention provides a highly doped semiconductor layer. More specifically, the present invention provides a semiconductor layer that includes at least two impurities. Each impurity is introduced at a level below its respective degradation concentration. I... | 04/27/2010 |
| 7645666 | Method of making a semiconductor device One or more embodiments relate to a method of making a heterojunction bipolar transistor (HBT) structure. The method includes: forming a partially completed heterojunction bipolar transistor (HBT) structure where the partially completed heterojunction bipolar transi... | 01/12/2010 |
| 7618858 | Method of fabricating a heterojunction bipolar transistor The invention provides a method for fabricating a heterojunction bipolar transistor with a base connecting region (23), which is formed self-aligned to a base region (7) without applying photolithographic techniques. Further, a collector connecting reg... | 11/17/2009 |
| 7601584 | Semiconductor array and method for manufacturing a semiconductor array A method for manufacturing a semiconductor array, particularly a high-frequency bipolar transistor, is provided, the method includes process steps, so that a dielectric is produced on a mono-crystalline, first semiconductor region of a first conductivity type, a sil... | 10/13/2009 |
| 7435643 | Fabrication method of a dynamic random access memory A dynamic random access memory (DRAM) cell is described, including a semiconductor pillar on a substrate, a capacitor on a lower portion of a sidewall of the pillar, and a vertical transistor on an upper portion of the sidewall of the pillar. The capacitor includes ... | 10/14/2008 |
| 7414298 | Super self-aligned collector device for mono-and hetero bipolar junction transistors, and method of making same The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the ... | 08/19/2008 |
| 7368401 | Integrated circuit having a doped porous dielectric and method of manufacturing the same In one aspect of the invention, a method for forming an integrated circuit having an at least substantially doped porous dielectric includes forming a semiconductor device. The semiconductor device includes at least a portion of a semiconductor substrate. The method... | 05/06/2008 |
| 7358132 | Self-aligned bipolar semiconductor device and fabrication method thereof A self-aligned bipolar semiconductor device and a fabrication method thereof are provided. After a silicon layer and a collector contact are formed on a buried collector layer, an oxide dummy pattern is formed on the silicon layer to define both an extrinsic base an... | 04/15/2008 |
| 7354820 | Heterojunction bipolar transistor with dielectric assisted planarized contacts and method for fabricating A method for fabricating an HBT is disclosed, wherein successive emitter, base, collector and sub-collector epitaxial layers are deposited on a substrate, with the substrate being adjacent to the sub-collector layer. The epitaxial layers are etched to provide locati... | 04/08/2008 |
| 7339254 | SOI substrate for integration of opto-electronics with SiGe BiCMOS According to an exemplary embodiment, a structure includes a silicon-on-insulator substrate including a buried oxide layer situated over a bulk silicon substrate and a silicon layer situated over the buried oxide layer. The structure further includes a trench formed... | 03/04/2008 |
| 7329552 | Field effect transistor fabrication methods, field emission device fabrication methods, and field emission device operational methods The present invention includes field effect transistors, field emission apparatuses, thin film transistors, and methods of forming field effect transistors. According to one embodiment, a field effect transistor includes a semiconductive layer configured to form a c... | 02/12/2008 |
| 7329583 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 02/12/2008 |
| 7319251 | Bipolar transistor A bipolar transistor formed in a substrate includes a collector, a base layer above the collector, where the base layer includes a base that is monocrystalline, and an emitter layer that is monocrystalline and above the base, where the emitter layer includes silicon... | 01/15/2008 |
| 7319274 | Methods for selective integration of airgaps and devices made by such methods Methods for the production of airgaps in semiconductor devices and devices produced using such methods are disclosed. An example semiconductor device includes a damascene stack formed using such methods. The damascene stack includes a patterned dielectric layer incl... | 01/15/2008 |
| 7304354 | Buried guard ring and radiation hardened isolation structures and fabrication methods Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isol... | 12/04/2007 |
| 7297589 | Transistor device and method A method for making a heterojunction bipolar transistor includes the following steps: forming a heterojunction bipolar transistor by depositing, on a substrate, subcollector, collector, base, and emitter regions of semiconductor material; the step of depositing the ... | 11/20/2007 |
| 7297993 | Bipolar transistor and fabrication method of the same A bipolar transistor having a base electrode of an air bridge structure is simplified in structure and enhanced in the degree of freedom of a contact position of a base wiring line with the base electrode. The bipolar transistor has a semiconductor mesa portion havi... | 11/20/2007 |
| 7294869 | Silicon germanium emitter Disclosed are an improved hetero-junction bipolar transistor (HBT) structure and a method of forming the structure that incorporates a silicon-germanium emitter layer with a graded germanium profile. The graded germanium concentration creates a quasi-drift field in ... | 11/13/2007 |
| 7285457 | Heterojunction bipolar transistor and manufacturing method thereof In the method for manufacturing a heterojunction bipolar transistor, a collector contact layer, a collector layer, a base layer, a base protection layer, an emitter layer, an emitter contact layer, and a WSi layer are sequentially formed on a substrate. A resist pat... | 10/23/2007 |
| 7282418 | Method for fabricating a self-aligned bipolar transistor without spacers According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a sacrificial post situated on the top surface of the base. The bipolar transistor also comprises a conformal layer situated o... | 10/16/2007 |
| 7279378 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/09/2007 |
| 7279399 | Method of forming isolated pocket in a semiconductor substrate A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 10/09/2007 |
| 7276431 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/02/2007 |
| 7276744 | Semiconductor device and method of manufacturing the same This invention is intended to provide an HBT capable of achieving, if the HBT is a collector-up HBT, the constriction of the emitter layer disposed directly under an external base layer, and reduction in base-emitter junction capacity, or if the HBT is an emitter-up... | 10/02/2007 |
| 7265434 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 09/04/2007 |
| 7265064 | Semiconductor device with porous interlayer insulating film In a method of manufacturing a semiconductor device, semiconductor circuit elements or wiring patterns are formed on a semiconductor substrate then, a porous semiconductor oxide film is formed as an interlayer insulating film on the semiconductor substrate including... | 09/04/2007 |
| 7247892 | Imaging array utilizing thyristor-based pixel elements An improved imaging array (and corresponding method of operation) includes a plurality of heterojunction thyristor-based pixel elements disposed within resonant cavities formed on a substrate. Each thyristor-based pixel element includes complementary n-type and p-ty... | 07/24/2007 |
