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| Number | Title | Issue Date |
| 8101480 | Methods of forming transistors and CMOS semiconductor devices using an SMT technique A method of forming a transistor induces stress in the channel region using a stress memorization technique (SMT). Impurities are implanted into a substrate adjacent a gate electrode structure to produce an amorphous region adjacent the channel region. The amorphous... | 01/24/2012 |
| 8101479 | Fabrication of asymmetric field-effect transistors using L-shaped spacers A gate electrode (302) of a field-effect transistor (102) is defined above, and vertically separated by a gate dielectric layer (300) from, a channel-zone portion (284) of body material of a semiconductor body. Semiconductor dopant is int... | 01/24/2012 |
| 8067283 | Semiconductor device fabricating method A semiconductor device fabricating method is described. The semiconductor device fabricating method includes providing a substrate. A first gate insulating layer and a second gate insulating layer are formed on the substrate, respectively. A gate layer is blanketly ... | 11/29/2011 |
| 8039341 | Selective uniaxial stress modification for use with strained silicon on insulator integrated circuit A semiconductor fabrication process includes masking a first region, e.g., an NMOS region, of a semiconductor wafer, e.g., a biaxial, tensile strained silicon on insulator (SOI) wafer and creating recesses in source/drain regions of a second wafer region, e.g., a PM... | 10/18/2011 |
| 8039342 | Enhanced integrity of a high-K metal gate electrode structure by using a sacrificial spacer for cap removal In a process strategy for forming sophisticated high-k metal gate electrode structures in an early manufacturing phase, the dielectric cap material may be removed on the basis of a protective spacer element, thereby ensuring integrity of a silicon nitride sidewall s... | 10/18/2011 |
| 8017473 | Modifying work function in PMOS devices by counter-doping A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semico... | 09/13/2011 |
| 8003460 | Method of forming a semiconductor structure comprising a formation of at least one sidewall spacer structure According to an illustrative example, a method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first feature and a second feature. A material layer is formed over the first feature and the second feature. A mask is for... | 08/23/2011 |
| 7935593 | Stress optimization in dual embedded epitaxially grown semiconductor processing Embodiments of the present disclosure provide stress optimization during manufacturing of dual embedded epitaxially grown (EPI) semiconductor structures using just two masks, such as nFET and pFET open for embedded epitaxial using SiC and SiGe, and separated halo im... | 05/03/2011 |
| 7897451 | Method for creating tensile strain by selectively applying stress memorization techniques to NMOS transistors By selectively applying a stress memorization technique to N-channel transistors, a significant improvement of transistor performance may be achieved. High selectivity in applying the stress memorization approach may be accomplished by substantially maintaining the ... | 03/01/2011 |
| 7888198 | Method of fabricating a MOS transistor with double sidewall spacers in a peripheral region and single sidewall spacers in a cell region An improved source/drain junction configuration in a metal-oxide semiconductor transistor is provided, as well as a novel method for fabricating this junction. This configuration employs gate double sidewall spacers in the peripheral region and gate single sidewall ... | 02/15/2011 |
| 7776680 | Complementary metal oxide semiconductor device with an electroplated metal replacement gate Disclosed herein are embodiments of a method of forming a complementary metal oxide semiconductor (CMOS) device that has at least one high aspect ratio gate structure with a void-free and seam-free metal gate conductor layer positioned on top of a relatively thin hi... | 08/17/2010 |
| 7736968 | Reducing poly-depletion through co-implanting carbon and nitrogen A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer over the semiconductor substrate; forming a gate electrode layer over the gate dielectric layer; doping carbon and nitrogen into the gate ele... | 06/15/2010 |
| 7696038 | Methods for fabricating flash memory devices Methods for fabricating flash memory devices are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises forming a first gate stack and a second gate stack overlying a substrate. A trench is etched in... | 04/13/2010 |
| 7696039 | Method of fabricating semiconductor device employing selectivity poly deposition A method for fabricating a semiconductor device employing a selectivity poly deposition is disclosed. The disclosed method comprises depositing selectivity poly on a gate poly and source/drain regions of the silicon substrate, and forming salicide regions on the gat... | 04/13/2010 |
| 7666736 | Method for fabricating semiconductor device comprising P-type MISFET, including step of implanting fluorine After the implantation of fluorine ions into a semiconductor substrate, a gate insulating film, a gate electrode and a protective film are formed on the semiconductor substrate. Thereafter, fluorine ions are again implanted into the semiconductor substrate. Furtherm... | 02/23/2010 |
| 7629216 | Method for fabricating CMOS image sensor with plasma damage-free photodiode A method for fabricating a complementary metal-oxide semiconductor (CMOS) image sensor includes providing a semi-finished substrate, forming a patterned blocking layer over a photodiode region of the substrate, implanting impurities on regions other than the photodi... | 12/08/2009 |
| 7601583 | Transistor structure of memory device and method for fabricating the same A memory device includes an active area protruding from a semiconductor substrate. A recess is formed in the active area. A field oxide layer is formed on the semiconductor substrate. A gate electrode extends across the active area while being overlapped with the re... | 10/13/2009 |
| 7582523 | Method of manufacturing semiconductor device including insulated-gate field-effect transistors A method of manufacturing a semiconductor device including MOS transistors is disclosed. N-type and p-type semiconductor films are formed respectively above first and second surface regions of a semiconductor substrate. First and second protective films are laminate... | 09/01/2009 |
| 7494862 | Methods for uniform doping of non-planar transistor structures Methods for uniformly tip doping a silicon body of a non-planar transistor and devices and systems formed by such methods. In one embodiment, a method can include vertical tip ion implantation of a silicon body with at least three surfaces on a substrate followed by... | 02/24/2009 |
| 7473595 | Method for decreasing PN junction leakage current of dynamic random access memory A method for decreasing a PN junction leakage current of a dynamic random access memory (DRAM), including the steps of: preparing an NMOS transistor formed on a P-type silicon substrate and comprising a drain; forming an insulation oxide layer on the P-type silicon ... | 01/06/2009 |
| 7456062 | Method of forming a semiconductor device A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer str... | 11/25/2008 |
| 7439123 | Low resistance contact semiconductor device structure A method for making a semiconductor device structure includes producing a substrate having formed thereon a gate with spacers, respective source and drain regions adjacent to the gate and an; disposing a first metallic layer on the gate with spacers, and the source ... | 10/21/2008 |
| 7439124 | Method of manufacturing a semiconductor device and semiconductor device Method of manufacturing a semiconductor device includes: forming a substrate protection film to cover an n-type FET forming region having a first gate electrode and a p-type FET forming region having a second gate electrode; opening the p-type FET forming region by ... | 10/21/2008 |
| 7432570 | Semiconductor device and manufacturing method thereof A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111... | 10/07/2008 |
| 7432144 | Method for forming a transistor for reducing a channel length A method of forming a transistor including: forming a gate oxide layer pattern and gate polysilicon layer pattern on a silicon substrate; forming a low energy ion implantation region aligned with both sidewalls of the gate polysilicon layer pattern; forming an amorp... | 10/07/2008 |
| 7413946 | Formation of standard voltage threshold and low voltage threshold MOSFET devices Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within... | 08/19/2008 |
| 7410859 | Stressed MOS device and method for its fabrication A stressed MOS device and a method for its fabrication are provided. The MOS device comprises a substrate having a surface, the substrate comprising a monocrystalline semiconductor material having a first lattice constant. A channel region is formed of the monocryst... | 08/12/2008 |
| 7402485 | Method of forming a semiconductor device A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer str... | 07/22/2008 |
| 7402484 | Methods for forming a field effect transistor Methods for forming a field effect transistor are disclosed. An illustrated method comprises: forming a gate electrode on a substrate; and forming a nitride layer on at least a part of the gate electrode and the substrate. ... | 07/22/2008 |
| 7390711 | MOS transistor and manufacturing method thereof A MOS transistor including a gate insulation layer and a gate electrode layer on a channel region of a semiconductor substrate. A gate spacer layer is formed on a sidewall of the electrode layer and the insulation layer. The transistor includes a deep extended sourc... | 06/24/2008 |
| 7390719 | Method of manufacturing a semiconductor device having a dual gate structure A semiconductor device having a dual gate is formed on a substrate having a dielectric layer. A first metallic conductive layer is formed on the dielectric layer to a first thickness, and annealed to have a reduced etching rate. A second metallic conductive layer is... | 06/24/2008 |
| 7384839 | SRAM cell with asymmetrical transistors for reduced leakage A method of fabricating an SRAM cell with reduced leakage is disclosed. The method comprises fabricating asymmetrical transistors in the SRAM cell. The transistors are asymmetrical in a manner that reduces the drain leakage current of the transistors. The fabricatio... | 06/10/2008 |
| 7378305 | Semiconductor integrated circuit and fabrication process thereof A semiconductor integrated circuit device includes an n-channel MOS transistor formed on a first device region of a silicon substrate and a p-channel MOS transistor formed on a second device region of the silicon substrate, wherein the n-channel MOS transistor inclu... | 05/27/2008 |
| 7378308 | CMOS devices with improved gap-filling A semiconductor structure includes a substrate, and a first MOS device on the first region of the substrate wherein the first MOS device includes a first spacer liner. The semiconductor structure further includes a second MOS device on the second region wherein the ... | 05/27/2008 |
| 7371647 | Methods of forming transistors The invention encompasses a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nit... | 05/13/2008 |
| 7371646 | Manufacture of insulated gate type field effect transistor After a field insulating film having an element opening is formed on the surface of a p-type well, a gate insulating film is formed on a semiconductor surface in the element opening. A gate electrode layer of polysilicon or the like is formed on the insulating film.... | 05/13/2008 |
| 7371691 | Silicon recess improvement through improved post implant resist removal and cleans The present invention provides a process of manufacturing a semiconductor device 200 while reducing silicon loss. In one aspect, the process includes removing a photoresist layer 270 from a semiconductor substrate 235 adjacent a gate 240 ... | 05/13/2008 |
| 7368792 | MOS transistor with elevated source/drain structure In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is fo... | 05/06/2008 |
| 7361539 | Dual stress liner A semiconductor device structure is provided which includes a first field effect transistor (“FET”) having a first channel region, a first source region, a first drain region and a first gate conductor overlying the first channel region. A second FET is included... | 04/22/2008 |
| 7358168 | Ion implantation method for forming a shallow junction A shallow junction that previously would require the use of a low-energy ion implanter can be directly formed by high-energy or middle-energy ion implanters such that the manufacturer need not purchase a new low-energy ion implanter. In one embodiment, an ion-implan... | 04/15/2008 |
