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| Number | Title | Issue Date |
| 8110414 | Forming integrated circuit devices with metal-insulator-metal capacitors using selective etch of top electrodes A method of forming integrated circuits (IC) having at least one metal insulator metal (MIM) capacitor. A bottom electrode is formed on a predetermined region of a semiconductor surface of a substrate. At least one dielectric layer including silicon is formed on the... | 02/07/2012 |
| 8093072 | Substrate processing apparatus and method of manufacturing semiconductor device Provided are a substrate processing apparatus and a method of manufacturing a semiconductor device, in which shape variations of discharge electrodes can be early detected so as to prevent a film having a non-uniform thickness from being formed on a substrate. The s... | 01/10/2012 |
| 8093073 | Manufacturing method of a tray, a socket for inspection, and a semiconductor device The yield of semiconductor devices is to be enhanced. A tray is provided with a plurality of pockets each capable of accommodating a wafer level CSP, and each of the pockets is provided with a base for supporting a plurality of bumps of the wafer level CSP and side ... | 01/10/2012 |
| 8084278 | Method of manufacturing silicon carbide semiconductor device A wafer WF is mounted in a substrate holder, and the substrate holder is placed in a film forming furnace. The film forming furnace is evacuated by a vacuum pump through a gas discharge part to remove remaining oxygen as completely as possible. Then, a temperature i... | 12/27/2011 |
| 8084277 | Semiconductor device and manufacturing method thereof A semiconductor device and manufacturing method thereof improving moisture resistance of a FeRAM. After a probe test using a pad, a metal film is formed to cover the pad in an opening of a protective film and a region from the pad to an opening outer periphery of th... | 12/27/2011 |
| 8062910 | Measurement of a sample using multiple models A sample that is processed to remove a top layer, e.g., using chemical mechanical polishing or etching, is accurately measured using multiple models of the sample. The multiple models may be constrained based on a pre-processing measurement of the sample. By way of ... | 11/22/2011 |
| 8063656 | Method of enabling a circuit board analysis A method of enabling a circuit board analysis is disclosed. The method comprising removing a portion of the circuit board on a first side of the circuit board opposite a second side of the circuit board having an integrated circuit package; removing the circuit boar... | 11/22/2011 |
| 8053255 | STRAM with compensation element and method of making the same Spin-transfer torque memory having a compensation element is disclosed. A spin-transfer torque memory unit includes a free magnetic layer having a magnetic easy axis and a magnetization orientation that can change direction due to spin-torque transfer when a write c... | 11/08/2011 |
| 8053256 | Variable thickness single mask etch process The present invention relates to a method of performing a variable film etch using a variable thickness photomask material. Essentially, a thickness of an adjustable film layer is measured and converted into a contour map of film thickness over a region of a semicon... | 11/08/2011 |
| 8051392 | Performance-aware logic operations for generating masks A method for forming masks for manufacturing a circuit includes providing a design of the circuit, wherein the circuit comprises a device; performing a first logic operation to determine a first region for forming a first feature of the device; and performing a seco... | 11/01/2011 |
| 8048688 | Method and apparatus for evaluation and improvement of mechanical and thermal properties of CNT/CNF arrays A method and apparatus for the evaluation and improvement of the mechanical and thermal properties of carbon-nanotube (CNT) and carbon nanofiber (CNF) arrays grown on a substrate is disclosed. The Young's modulus of a CNT/CNF material is measured by applying an axia... | 11/01/2011 |
| 8048689 | Semiconductor chip with backside conductor structure Various semiconductor devices and methods of testing such devices are disclosed. In one aspect, a method of manufacturing is provided that includes forming a bore from a backside of a semiconductor chip through a buried insulating layer and to a semiconductor device... | 11/01/2011 |
| 8034640 | Apparatus and method to inspect defect of semiconductor device An apparatus and method to inspect a defect of a semiconductor device. The amount of secondary electrons generated due to a scanning electron microscope (SEM) may depend on the topology of a pattern of a semiconductor substrate. The amount of secondary electrons emi... | 10/11/2011 |
| 8026113 | Method of monitoring a semiconductor processing system using a wireless sensor network A method and system for non-invasive sensing and monitoring of a processing system employed in semiconductor manufacturing. The method allows for detecting and diagnosing drift and failures in the processing system and taking the appropriate correcting measures. The... | 09/27/2011 |
| 8021898 | Method and apparatus for controlled thermal processing A materials processing system comprises a thermal processing chamber including a heating source, a first noncontacting thermal measurement device positioned to measure temperature on a first area of the material being processed, and, a second noncontacting thermal m... | 09/20/2011 |
| 8017411 | Dynamic adaptive sampling rate for model prediction A method and an apparatus for dynamically adjusting a sampling rate relating to wafer examination. A process step is performed upon a plurality of workpieces associated with a lot. A sample rate for acquiring metrology data relating to at least one of the processed ... | 09/13/2011 |
| 7989230 | Method for PMOS device processing using a polysilicon footing characteristic to achieve low leakage A method for manufacturing a MOS device. The method includes providing a semiconductor substrate. The method forms a gate dielectric layer overlying the semiconductor substrate and a polysilicon gate overlying the gate dielectric layer. The polysilicon gate is chara... | 08/02/2011 |
| 7989228 | Method and structure for sample preparation for scanning electron microscopes in integrated circuit manufacturing A method for using a calibration standard. The method includes providing a calibration standard. In a specific embodiment, the calibration standard has a substrate, a thickness of material having an edge region; and a conformal material of uniform thickness disposed... | 08/02/2011 |
| 7989229 | Tactile surface inspection during device fabrication or assembly Processes for inspecting a surface during device fabrication include contacting the surface with a tactile sensor. The tactile sensor is an electroluminescent tactile sensor array or a current electrode sensor array or a capacitive sensor array. The sensor is config... | 08/02/2011 |
| 7972874 | Semiconductor process evaluation methods including variable ion implanting conditions Semiconductor process evaluation methods perform multiple scans of a test semiconductor substrate (e.g., test wafer) using ion beams under different ion implanting conditions. Parameters of the test semiconductor substrate that was scanned using the ion beams under ... | 07/05/2011 |
| 7968354 | Methods for correlating backside and frontside defects detected on a specimen and classification of backside defects Computer-implemented methods that include correlating a backside defect with a frontside defect detected on a specimen are provided. The defects are correlated if a portion of the backside defect on the backside of the specimen is opposite to a portion of the fronts... | 06/28/2011 |
| 7964418 | Real time process monitoring and control for semiconductor junctions A method of manufacturing a semiconductor layer is provided. In a first deposition during a first period of time, at least one Group IIIA element and at least one Group VIA element are deposited on a substrate or on a layer optional disposed on the substrate such as... | 06/21/2011 |
| 7951616 | Process for wafer temperature verification in etch tools A blank wafer is placed in an etch chamber. A layer is deposited over the blank wafer, comprising providing a deposition gas, forming the deposition gas into a deposition plasma, and stopping the deposition gas. The blank wafer with the deposited layer is removed fr... | 05/31/2011 |
| 7951615 | System and method for implementing multi-resolution advanced process control One embodiment is a method for fabricating ICs from a semiconductor wafer. The method includes performing a first process on the semiconductor wafer; taking a first measurement indicative of an accuracy with which the first process was performed; and using the first... | 05/31/2011 |
| 7947514 | Semiconductor device production process A semiconductor device production process includes forming, on a prepared SOI wafer, semiconductor functional devices and substrate contacts. The substrate contacts connect to a support substrate of the SOI wafer. The semiconductor device production process also inc... | 05/24/2011 |
| 7947515 | Defect inspecting method A defect inspecting method includes: forming, in a first air pressure state, a film, which covers one opening of two openings provided on an upper surface of a substrate, on a tubular contact hole formed on the substrate in manufacturing a semiconductor device and f... | 05/24/2011 |
| 7935548 | Deposition apparatus and deposition method A deposition apparatus includes: a first electrode for placing a processing object; a second electrode for generating plasma with the first electrode, the second electrode being opposed to the first electrode; and a heat flow control heat transfer part for drawing h... | 05/03/2011 |
| 7935549 | Seminconductor device The present invention provides a signal transmitting/receiving method comprising: disposing a ferromagnetic film between a semiconductor device having an inductor and an external device which includes an external inductor provided in a position corresponding to the ... | 05/03/2011 |
| 7932103 | Integrated circuit system with MOS device An integrated circuit system includes measuring capacitance for a base structure between a base gate and a base connector thereof, measuring capacitance for a test structure between a test gate and a test connector thereof, the test structure having the test gate, a... | 04/26/2011 |
| 7932104 | Method for inspecting photoresist pattern A method for inspecting a photoresist pattern is disclosed. First, a substrate with a first doping region is provided. Then, a photoresist is formed to cover the substrate. Later, the photoresist is patterned to form a photoresist pattern. Afterwards, the substrate ... | 04/26/2011 |
| 7927893 | Method for treatment of samples for auger electronic spectrometer (AES) in the manufacture of integrated circuits A method for analyzing a sample for the manufacture of integrated circuits, e.g. MOS transistors, application specific integrated circuits, memory devices, microprocessors, system on a chip. The method includes providing an integrated circuit chip, which has a surfa... | 04/19/2011 |
| 7923266 | Design methodology for MuGFET ESD protection devices A method for manufacturing a MuGFET ESD protection device having a given layout by means of a given manufacturing process, the method comprising selecting multiple interdependent layout and process parameters of which a first set are fixed by said manufacturing proc... | 04/12/2011 |
| 7923265 | Method and system for improving critical dimension proximity control of patterns on a mask or wafer A method for improving critical dimension uniformity of a substrate is provided. An equation based on a proximity trend of a pattern on a first substrate is determined. The equation is applied in a regression model to determine a parameter value of a second substrat... | 04/12/2011 |
| 7919335 | Formation of shallow trench isolation using chemical vapor etch A method includes measuring a depth of a shallow trench isolation (STI) region below a surface of a substrate. The STI region is filled with an oxide material. The substrate has a nitride layer above the surface. A thickness of the nitride layer is measured. A first... | 04/05/2011 |
| 7915056 | Image sensor monitor structure in scribe area A semiconductor die including a semiconductor chip and a test structure, located in a scribe area, is designed and manufactured. The test structure includes an array of complementary metal oxide semiconductor (CMOS) image sensors that are of the same type as CMOS im... | 03/29/2011 |
| 7915057 | Manufacturing method of a tray, a socket for inspection, and a semiconductor device The yield of semiconductor devices is to be enhanced. A tray is provided with a plurality of pockets each capable of accommodating a wafer level CSP, and each of the pockets is provided with a base for supporting a plurality of bumps of the wafer level CSP and side ... | 03/29/2011 |
| 7917871 | Method and program for pattern data generation using a modification guide A pattern data generation method of an aspect of the present invention, the method includes creating at least one modification guide to modify a modification target point contained in pattern data, evaluating the modification guides on the basis of an evaluation ite... | 03/29/2011 |
| 7915055 | Manufacturing method of semiconductor device The present invention provides a manufacturing technique of a semiconductor device that reduces fluctuation of electric characteristic and a working size of a semiconductor device and can manufacture semiconductor devices at high quality and at high yield. In a semi... | 03/29/2011 |
| 7906350 | Method for calibrating a metrology tool A method and apparatus for calibrating a metrology tool are disclosed. The apparatus includes a substrate having at least one calibration site formed thereon. The calibration site includes a pattern of cells that have at least one feature disposed in a surface of th... | 03/15/2011 |
| 7906348 | Method of feed forward control of scanned rapid thermal processing A thermal processing system and method including scanning a line beam of intense radiation in a direction transverse to the line direction for thermally processing a wafer with a localized effectively pulsed beam of radiant energy. The thickness of the wafer is two-... | 03/15/2011 |