Celebrity Inventors
Comic actor Danny Kaye received patent D166,807 for the co-design of "Blowout Toy or the Like". It's similar to one of those toys that unravels when you blow into at a birthday party except Kaye's has three blowouts going in different directions, not just one.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8420411 | Method for aligning wafer stack A method for aligning a wafer stack includes providing a wafer stack including a top wafer with a top mark and a bottom wafer with a bottom mark in particular the top mark and the bottom mark capable of corresponding to each other; adjusting a relative position betw... | 04/16/2013 |
| 8378698 | Integrated circuit testing apparatus and method A testing apparatus includes a test controller configured to output a plurality of chip selection signals for selecting chips to be tested from among a plurality of chips, a plurality of first control signals for controlling supply of a power supply voltage to the c... | 02/19/2013 |
| 7807480 | Test cells for semiconductor yield improvement A test cell for localizing defects includes a first active region, a second active region formed substantially parallel to the first active region, a third active region formed substantially parallel to the first and second active regions, a fourth active region for... | 10/05/2010 |
| 7799583 | System for separation of an electrically conductive connection An integrated component includes a semiconductor substrate; at least one interconnect applied on the semiconductor substrate; an insulating layer applied on the at least one interconnect; and at least one opening through the insulating layer which interrupts the at ... | 09/21/2010 |
| 7745235 | Method for manufacturing semiconductor sensor A semiconductor sensor is disclosed that includes a substrate including at least a semiconductor layer. The substrate includes a weight arranging part in the vicinity of the center of the substrate, a flexible part around the weight arranging part, and supporting pa... | 06/29/2010 |
| 7736916 | System and apparatus for using test structures inside of a chip during the fabrication of the chip The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performa... | 06/15/2010 |
| 7662647 | Method for manufacturing semiconductor device A burn-in input signal input to a burn-in circuit is delivered to an internal circuit through a selector. In response to a control signal from the burn-in circuit, the selector selects either the burn-in input signal or an input signal for operating the internal cir... | 02/16/2010 |
| 7648847 | In-situ monitoring and method to determine accumulated printed wiring board thermal and/or vibration stress fatigue using a mirrored monitor chip and continuity circuit A monitoring system includes a monitor chip or chips soldered to a printed wiring board. By mirroring a function IC chip interface with the monitor chip, the consumed and remaining thermal/and or vibration-fatigue life of the function IC chip based on the life-envir... | 01/19/2010 |
| 7510884 | Semiconductor production system and semiconductor production process A semiconductor manufacturing apparatus according to the present invention comprises: a treating unit that treats a substrate to manufacture thereon a semiconductor device; a fluid supplying channel for supplying a fluid required for a treatment of the substrate to ... | 03/31/2009 |
| 7498180 | Method for manufacturing semiconductor device A burn-in input signal input to a burn-in circuit is delivered to an internal circuit through a selector. In response to a control signal from the burn-in circuit, the selector selects either the burn-in input signal or an input signal for operating the internal cir... | 03/03/2009 |
| 7425458 | Selectable decoupling capacitors for integrated circuits and associated methods Selectable capacitors are used to modify performance characteristics of functional circuit elements of an integrated circuit (IC). In an embodiment, the decoupling capacitors are implemented as additional or alternative mounting pads on a surface of the IC. At least... | 09/16/2008 |
| 7423288 | Technique for evaluating a fabrication of a die and wafer The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performa... | 09/09/2008 |
| 7422913 | Method for checking a condition of a heat treatment A method for connecting terminals is provided. The method includes steps of a) providing a board having a first terminal thereon; b) performing a check of a heat treatment by using a thermal sensitive paper in order to determine a optimal condition of the heat treat... | 09/09/2008 |
| 7405414 | Method and apparatus for patterning a workpiece The present invention relates to a method for creating a pattern on a workpiece sensitive to electromagnetic radiation. Electromagnetic radiation is emitted onto a computer controlled reticle having a multitude of modulating elements (pixels). The pixels are arrange... | 07/29/2008 |
| 7402801 | Inspecting method of a defect inspection device An inspecting method comprises the following steps. A plurality of defect inspection devices is formed on a wafer. Each defect inspection device comprises an insulating layer and a conductive layer stacked over the insulating layer. A defect inspection parameter is ... | 07/22/2008 |
| 7393703 | Method for reducing within chip device parameter variations A method of reducing parametric variation in an integrated circuit (IC) chip and an IC chip with reduced parametric variation. The method includes: on a first wafer having a first arrangement of chips, each IC chip divided into a second arrangement of regions, measu... | 07/01/2008 |
| 7395518 | Back end of line clone test vehicle A test vehicle comprises at least one product layer having a east one product circuit pattern on the product layer, and one or more clone layers formed over the product layer (1902). The one or more clone layers include a plurality of structures, which may in... | 07/01/2008 |
| 7391023 | Lithography tool image quality evaluating and correcting Electron beam lithography tool image quality evaluating and correcting including a test pattern with a repeated test pattern cell, an evaluation method and correction program product are disclosed. The test pattern cell includes a set of at least three elongated spa... | 06/24/2008 |
| 7390682 | Method for testing metal-insulator-metal capacitor structures under high temperature at wafer level A test methodology is provided for testing metal-insulator-metal (MIM) capacitor structures under high temperatures at the wafer level. A resistor is formed on a region of dielectric isolation material formed in a semiconductor substrate. The MIM capacitor is formed... | 06/24/2008 |
| 7378289 | Method for forming photomask having test patterns in blading areas A photomask and a method for forming a photomask are disclosed in which die regions that define features for a process step of a semiconductor fabrication process are formed on a photomask and a test pattern for a different process step is formed in a blading area o... | 05/27/2008 |
| 7378290 | Isolation circuit An isolation circuit includes a first pad adapted to receive a control signal and a second pad adapted to receive another signal. A third pad is coupled to a microelectronic die and a device is provided to transfer the other signal from the second pad to the third p... | 05/27/2008 |
| 7372072 | Semiconductor wafer with test structure The invention relates to a semiconductor wafer (1) having a plurality of first sawing regions (201-211) running parallel to one another in a first direction (X) and a plurality of second sawing regions (301-311) running parallel to... | 05/13/2008 |
| 7373216 | Method and apparatus for verifying a site-dependent wafer The present invention includes a method of verifying a Site-Dependent (S-D) wafer that includes receiving a first set of S-D wafers by one or more S-D processing elements in one or more processing subsystems, creating a first set of unverified S-D wafers by performi... | 05/13/2008 |
| 7368304 | Fabricating die with separate test pads selectively coupled to cores Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits w... | 05/06/2008 |
| 7353481 | Computer implemented method for designing a semiconductor integrated circuit and a semiconductor integrated circuit A computer implemented method for designing a semiconductor integrated circuit includes placing dummy pattern on a second interconnection layer positioned just above the first power line based on a placement result of the first power line, the dummy pattern having a... | 04/01/2008 |
| 7339963 | High speed data channel including a CMOS VCSEL driver and a high performance photodetector and CMOS photoreceiver A high speed optical channel including an optical driver and a photodetector in a CMOS photoreceiver. The optical channel driver includes a FET driver circuit driving a passive element (e.g., an integrated loop inductor) and a vertical cavity surface emitting laser ... | 03/04/2008 |
| 7339388 | Intra-clip power and test signal generation for use with test structures on wafers The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performa... | 03/04/2008 |
| 7335518 | Method for manufacturing semiconductor device In a manufacturing method for a semiconductor device, a main body wafer is formed, and a monitor wafer on which a monitor element is formed is provided. Characteristics of the main body wafer are copied onto the monitor element by simultaneously processing the main ... | 02/26/2008 |
| 7332360 | Early detection of metal wiring reliability using a noise spectrum The present invention generally provides an apparatus and a method for inspecting a substrate in a substrate processing system. In one aspect, a voltage or current source is used in conjunction with a power density receiving device, such as a spectrometer, to inspec... | 02/19/2008 |
| 7316935 | Reticle for layout modification of wafer test structure areas Techniques are provided for forming die on wafers with large area test structures between primary die. A reticle is used to pattern each die. The pattern on the reticle forms a primary die and test structures in scribelines that abut edges of the die. A reticle can ... | 01/08/2008 |
| 7309920 | Chip structure and process for forming the same A chip or wafer comprises a semiconductor substrate, first and second transistors on the semiconductor substrate, first and second metal layers over the semiconductor substrate, an insulating layer on the first and second metal layers, a third and fourth metal layer... | 12/18/2007 |
| 7301239 | Wiring structure to minimize stress induced void formation A wiring structure with improved resistance to void formation and a method of making the same are described. The wiring structure has a first conducting layer that includes a large area portion which is connected to an end of a protrusion with a plurality of “n”... | 11/27/2007 |
| 7301225 | Multi-row lead frame A lead frame (10) for a semiconductor device includes a first row of terminals (12) surrounding a die receiving area (14) and a second row of terminals (16) spaced from and surrounding the first row of terminals (12). The first and... | 11/27/2007 |
| 7299818 | Integrated microvalve and method for manufacturing a microvalve An integrated microvalve has a substrate, a first function layer applied to the substrate, and a second function layer applied to the first function layer, the first function layer being designed as a diaphragm in at least one valve area, the second function layer b... | 11/27/2007 |
| 7294911 | Ultrathin leadframe BGA circuit package A circuit package is formed using a leadframe. The leadframe is formed or etched to align a plurality of bond pad structures above a reference plane while supporting leadframe fingers are positioned below the reference plane. Jumper wires are wirebonded between term... | 11/13/2007 |
| 7292335 | Optical measurements of patterned structures A method and a system for optical measuring in a structure having a pattern in the form of spaced-apart parallel elongated regions of optical properties different from that of spaces between said regions. The system comprises a broadband illuminator (8) for g... | 11/06/2007 |
| 7290190 | Semiconductor integrated circuit with a test circuit A shift scan chain includes logic circuit blocks 11-18 and scan registers 21-28 connected at stages succeeding them. The shift chain is divided into divisional chains including the scan registers 21-24 and the scan registers... | 10/30/2007 |
| 7285849 | Semiconductor die package using leadframe and clip and method of manufacturing A clip structure for a semiconductor package is disclosed. The clip structure includes a major portion, at least one pedestal extending from the major portion, a downset portion, and a lead portion. The downset portion is between the lead portion and the major porti... | 10/23/2007 |
| 7282374 | Method and apparatus for comparing device and non-device structures The present invention provides a method and apparatus for comparing device and non-device structures. The method includes determining at least one characteristic parameter associated with at least one non-device structure on at least one workpiece and determining at... | 10/16/2007 |
| 7282376 | System, method, and apparatus for electrically testing lead-to-lead shorting during magnetoresistive sensor fabrication Built-in electrical test structures are measured for lead-to-lead shorting during the fabrication of MR elements on a wafer. The test structures are fabricated in the same fashion as the MR elements, however, the active sensor region or track width is omitted from t... | 10/16/2007 |
