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| Number | Title | Issue Date |
| 8116425 | Shift register A shift register includes a first flip-flop group composed of a plurality of cascaded first flip-flops, each first flip-flop having a first master latch and a first slave latch and having first and second transmission paths for transmitting a master clock and a slav... | 02/14/2012 |
| 8000432 | Shift register A shift register includes a first flip-flop group composed of a plurality of cascaded first flip-flops, each first flip-flop having a first master latch and a first slave latch and having first and second transmission paths for transmitting a master clock and a slav... | 08/16/2011 |
| 7873140 | Shift register A shift register is disclosed. The shift register includes a plurality of stages for sequentially outputting scan pulses, wherein each of the stages includes a scan pulse output unit controlled according to voltage states of a set node and reset node for outputting ... | 01/18/2011 |
| 7271793 | Liquid crystal display device, driving method for liquid crystal display devices, and inspection method for liquid crystal display devices Using technology which uses a single shift register and simultaneously generates multiple pulses, this invention is a liquid crystal display device which rapidly drives data lines. It is possible to increase the frequency of the shift register output signal without ... | 09/18/2007 |
| 7177385 | Shift register for safely providing a configuration bit The invention relates to a shift register cell for safely providing a configuration bit having a master latch which can be connected to a serial data input on the shift register cell for the purpose of buffer storing a data bit; a first slave latch which can be conn... | 02/13/2007 |
| 7042973 | Variable dividing circuit To provide a variable dividing circuit having a high operational speed. The variable dividing circuit includes a shift register configured by cascade connection of D-type flip-flops (D11, D12, . . . , D1n) with an initializing means by clock syn... | 05/09/2006 |
| 7042895 | Method and apparatus for interfacing multiple communication devices to a time division multiplexing bus A time division multiplexing (TDM) method and apparatus for interfacing data from communication channels to a TDM bus. The TDM arrangement uses a shift register to control a tri-state buffer. The shift register regulates the tri-state buffer based on a data bit patt... | 05/09/2006 |
| 6795000 | Programmable converter having an automatic channel sequencing mode A counter circuit is provided which is particularly suitable for controlling cyclical events. The counter consists of a chain of logic elements 160, 167, 164 which sequentially pass a ‘1’ along the chain in response to a clock signal. Each element is also... | 09/21/2004 |
| 6249238 | Sigma-delta modulator and method for suppressing a quantization error in a sigma-delta modulator A sigma-delta modulator is disclosed for conversion of an analog or digital low frequency signal of high resolution into a quantized analog or digital signal, with an error feedback circuit for suppression of quantization errors. The sigma-delta modulator... | 06/19/2001 |
| 6057720 | High speed sticky signal generator The present invention has been made in view of the above mentioned problem, and the present invention provides a sticky signal generator for rapidly generating a sticky signal with a small layout area which uses a shift register of which the size is equal... | 05/02/2000 |
| 5804987 | LSI chip having programmable buffer circuit An LSI chip is mounted on an LSI board. Sub-buffer circuit areas where input buffers, output buffers or input/output buffers are to be formed are provided in signal lines extending from the pad to the internal circuit of the LSI chip. Each sub-buffer circ... | 09/08/1998 |
| 5761265 | Parallel architecture for generating pseudo-random sequences A parallel architecture for implementing a digital sequence generator is provided, which contains taps connected to selected fixed memory cells and the taps of the logic circuitry are switched among the cells. The architecture disclosed and claimed herein... | 06/02/1998 |
| 5517542 | Shift register with a transistor operating in a low duty cycle A shift register for scanning a liquid crystal display includes cascaded stages. A given stage is formed with an input transistor switch that is responsive to an output pulse of a stage upstream in the chain of the cascaded stages. An output pulse of the ... | 05/14/1996 |
| 5512846 | Signal selecting device controlled by a serially transmitted mode signal requiring but one terminal In a signal selecting device, a mode determination portion 61 comprises a shift register 11, a clock generating portion 20 and decoder 51. The clock generating portion 20 receives a mode signal M and generates a clock signal CK1 used for decoding the mode... | 04/30/1996 |
| 5400050 | Driving circuit for use in a display apparatus A driving circuit for use in a display apparatus for transmitting a video signal to data lines includes a plurality of shift registers; a control signal generating circuit for outputting a control signal which is at the ON level during a period shorter th... | 03/21/1995 |
| 5377248 | Successive-approximation register A successive-approximation register (SAR) has a single shift register for processing, that is presetting and selectively resetting, a number of bits. The single shift register is arranged to provide bit selection for processing the bits and also to provid... | 12/27/1994 |
| 5363424 | Partially-operable driver circuit A driver circuit comprising an output level selection circuit and a shift register is disclosed. The output level selection circuit has driving terminals, potential level input terminals and data input terminals, and an output signal having one of the dif... | 11/08/1994 |
| 5355037 | High performance digital phase locked loop A first periodic digital waveform is to be synchronized with a second periodic digital waveform obtained by propagating the first waveform through a delay path (13) having an adjustable propagation delay. In the disclosed approach, the delay of the delay ... | 10/11/1994 |
| 5335254 | Shift register system for driving active matrix display A clock control circuit for sequentially enabling the clock input terminal of a number of groups of shift register stages for reducing the power consumption. The groups are seccessively activated, and the groups currently not in operation are made not to ... | 08/02/1994 |
| 5295174 | Shifting circuit and shift register A shift register comprises a plurality of latch circuits for latching time series signals inputted thereto, a multiplexer for selecting outputs of the latch circuits in sequence, and a clock control circuit for generating clocks used for controlling selec... | 03/15/1994 |
| 5233637 | System for generating an analog regulating voltage A system for generating an analog regulating voltage to be supplied to one or more circuit elements on an integrated circuit. The circuit elements have operational characteristics that are voltage dependent and the analog regulating voltage having the a p... | 08/03/1993 |
| 5222082 | Shift register useful as a select line scanner for liquid crystal display A select line scanner for a liquid crystal display includes a plurality of cascaded stages each having an input terminal and an output terminal. Each stage includes an output circuit which switches the output terminal between high and low states. A first ... | 06/22/1993 |
| 5187725 | Data detector at output of counter A data detector comprises a counter having a plural-bit parallel output, compensation means for compensating a shift of output times of a low order bit and a high order bit of the counter caused by a carry signal from the low order bit to the high order b... | 02/16/1993 |
| 5164970 | Cascaded driver circuit A cascaded driver circuit has two or more stages connected to a common serial data signal line and a common clock pulse signal line. Each stage has a counter circuit for dividing the frequency of the clock pulse signal and an enable latch circuit for latc... | 11/17/1992 |
| 5155779 | Optical circulating shift register An all-optical circulating shift register encodes a received optical clock signal with a value derived from an encoded optical signal received at a control port thereof. A data input to the shift register is used to modify an encoded optical signal. The r... | 10/13/1992 |
| 5132993 | Shift register circuit A shift register circuit includes a logical operator which is added to an output terminal of a latch portion and takes a logical operation of input and output signals of the latch portion and outputs its result as a bit signal. The signal of a bit compone... | 07/21/1992 |
| 5099502 | Shift register for producing pulses in sequence Disclosed herewith is a shift register for shifting data in series in synchronism with a shift clock signal and is composed of a plurality of data-shift gages connected in cascade, each of which includes a shift-in terminal and a shift-out terminal, and e... | 03/24/1992 |
| 5063578 | Digital logic circuits for frequency multiplication A digital logic circuit (100) is provided for multiplying, such as doubling, the frequency of an input clock pulse sequence of period T. The circuit in one embodiment includes complementarily clocked first and second chains of cascaded delay elements (12,... | 11/05/1991 |
| 5060244 | Method and apparatus for indicating when the total in a counter reaches a given number In order to compare the total reached by a counter counting pulses from a source with a given number, the more significant digits from the counter are compared with the corresponding digits of the given number. The comparator produces an output when the g... | 10/22/1991 |
| 5055842 | Multi-stage serial-to-parallel/parallel-to-serial converter processing data words by segments A circuit for parallel-to-serial or serial-to-parallel conversion uses a multi-stage structure for conversion of long data words section-by-section. Each section of the data word corresponds to length/width of the respective registers or latches of the ci... | 10/08/1991 |
| 5036230 | CMOS clock-phase synthesizer An integrated circuit apparatus for changing the phase relationship between at least one clock-phase output and a reference clock is disclosed. The sequence control apparatus is coupled to a waveform synthesizer apparatus producing at least one clock-phas... | 07/30/1991 |
| 5027382 | Shift register circuit A shift register circuit comprises a series circuit comprising a plurality of first clocked gate inverters and inverters which are alternately connected in series, where a first one of the first clocked gate inverters is adapted to receive an input pulse ... | 06/25/1991 |
| 5016263 | Sample-hold circuit with outputs taken between gates of dynamic shift register to avoid skew from unequal interstage connection lengths A sample-hold circuit comprises a large number of sample-hold elements, and a multi-stage shift register for controlling sampling timings of the sample-hold elments, including a large number of stages corresponding to respective sample-hold elements, wher... | 05/14/1991 |
| 5003201 | Option/sequence selection circuit with sequence selection first A circuit is provided having a plurality of flip flops (Fl -Fn) that are serially connected for executing sequential operations under the control of a clock. The outputs (Ql -Qn) of the flip flops (Fl... | 03/26/1991 |
| 4977341 | Integrated circuit to reduce switching noise A transistor (14) having a plurality of sub-transistors (26a-f) includes a voltage controlling device (45). The voltage controlling device induces a current through an elongated gate (24) producing a voltage drop across the elongated gate (24) by providin... | 12/11/1990 |
| 4975605 | Synchronous delay line with automatic reset An automatic reset scheme for a synchronized delay line detects the polarity of the tap signals from a predetermined number of delay stages. If the delay line powers up to lock onto one of the non-fundamental modes of operation, an inverted polarity is de... | 12/04/1990 |
| 4958274 | System with a N stages timing silo and P stages information silo for soloing information A method and arrangement for siloing information in a computer system uses a smaller number of large-size latches by providing a timing silo having a set of n timing state devices sequentially connected for receiving and siloing at least one bit. The arra... | 09/18/1990 |
| 4945518 | Line memory for speed conversion A line memory for speed conversion, whose data rates of write into and read from a memory cell (1) differ from each other, has a write circuit (2, 3, 4) for writing input data (Din) into the cell (1) at a predetermined rate and resetting the wr... | 07/31/1990 |
| 4931986 | Computer system clock generator for generating tuned multiple clock signals A computer system clock generator generates several system clock signals which are in a tuned state at desired locations, thereby offsetting the effects of varying propagation delays among the system clock signals. A shift register ring has one of its tap... | 06/05/1990 |
| 4894626 | Variable length shift register A programmable computer shift register or other time delay means of variable length that provides time delays that are integral multiples of a predetermined time delay unit Ɗt, that uses relatively few switches, that controls time delays introduced by pa... | 01/16/1990 |
