Mark Twain (Samuel L. Clemens) received Patent No. 121,992 for "An Improvement in Adjustable and Detachable Straps for Garments." He later received two more patents: one for a self-pasting scrapbook and one for a game to help players remember important historical dates.
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| Number | Title | Issue Date |
| 7430268 | Dynamic shift register with built-in disable circuit A disable circuit for using in a dynamic shift register unit comprising: a first input, a second input, an output, a first reference line for receiving a first supply voltage, a second reference line for receiving a second supply voltage, and six transistors. The di... | 09/30/2008 |
| 7342991 | Shift register circuit A shift register without a feedback signal of a post-stage shift register utilizing a latch mechanism and a clock signal to control the voltage of an output of the shift register is provided. The shift register reduces the transistor size and the circuit layout area... | 03/11/2008 |
| 7317779 | Method of driving transistor and shift register performing the same A shift register has multiple stages each of which includes a pull-up part to generate a current gate line driving signal having a first state in response to a first control signal and a clock signal, a pull-down part to generate the current gate line driving signal... | 01/08/2008 |
| 6747627 | Redundancy shift register circuit for driver circuit in active matrix type liquid crystal display device In a shift register circuit included in a driver circuit for driving an active matrix circuit in an active matrix type display device, a plurality of serial-connected registers constructing register lines are arranged to construct a redundancy shift register circuit... | 06/08/2004 |
| 6611248 | Shift register and electronic apparatus Each of stages RS(1), RS(2), . . . of a shift register is constituted by six TFTs. A ratio of a channel width and a channel length (W/L) of each of these TFTs 1 to 6 is set in accordance with a transistor characteristic of each TFT in such a manner that t... | 08/26/2003 |
| 6549605 | Limiting loss in a circuit A circuit for limiting loss in a second circuit. The circuit may include a first timer, a second timer and one or more logic gates. The first timer may produce a first output in a given state if the duration of a pulse for use with the second circuit reac... | 04/15/2003 |
| 6490332 | High speed, low-power shift register and circuits and methods using the same A shift register includes a plurality of shift register stages having inputs and outputs coupled to form a chain. Each stage includes enable and disable control inputs, with an output of a selected one of the stages coupled to the enable input of a stage ... | 12/03/2002 |
| 5682340 | Low power consumption circuit and method of operation for implementing shifts and bit reversals The present invention describes a circuit (10) and associated method of operation for implementing bit reversals and shifts of an input data. The circuit (10) includes a plurality of input lines (12), a plurality of output lines (14), a plurality of shift... | 10/28/1997 |
| 5521953 | Shift register with transfer gate-inverter arrangement providing stable operation A shift register which is stably operable even under low power voltage and including a first transfer gate NTM1 connected to a data input terminal DIN1, second and third transfer gates NTM2 and NTM3 connected in series to a ground line, a pair of inverter... | 05/28/1996 |
| 5517543 | Circuit device for controlling circuit components connected in series or in a matrix-like network The circuit device has a plurality of cascaded stages. Each cascaded stage includes several partial stages and has at most two capacitors (Cn1, CnB) and at most seven transistors (Tn1, Tn2, Tn3, T | 05/14/1996 |
| 5170074 | Master-slave clocked flip-flop circuit A flip-flop of a master-slave type of a CMOS structure having no P channel transistor between nodes of the master flip-flop and of the slave flip-flop is provided. Only one P channel MOS transistor is existent in a route of the current controlling a rise ... | 12/08/1992 |
| 5148058 | Logic circuits as for amorphous silicon self-scanned matrix arrays A logic circuit includes pull-up and pull-down transistors and a capacitance, the principal conducting paths of the transistors and the capacitance being coupled in series between a first supply bus and a source of time varying potential. The pull-up tran... | 09/15/1992 |
| 4856034 | Semiconductor integrated circuit A semiconductor integrated circuit comprises a three-valued logic circuit connected to receive an output signal of a logic circuit to receive at one input a control clock signal and at the other input an input signal, and a flip-flop circuit composed of a... | 08/08/1989 |
| 4715052 | Frequency divide by N circuit A frequency divide by n circuit, where n is an odd number, which includes means for splitting an incoming clock signal of frequency "f" into two non-overlapping complementary clock signals of frequency "f" and a shift register circuit. The shift register ... | 12/22/1987 |
| 4677317 | High voltage signal output circuit provided with low voltage drive signal processing stages A high voltage signal producing circuit, such as a panel display driver, includes an input terminal receiving an input signal, a first signal processor receiving the input signal through a conductive line, a second signal processor receiving the input sig... | 06/30/1987 |
| 4651333 | Shift register memory cell having a transmission gate disposed between an inverter and a level shifter A shift register comprising a plurality of memory cells serially coupled together along a signal bus. Each one of the plurality of memory cells comprises a first amplifier, fed by an input logic signal, for amplifying and inverting the logic state of the ... | 03/17/1987 |
| 4418418 | Parallel-serial converter A parallel-serial converter comprises a plurality of selection-delay unit circuits. The unit circuit selectively receives an output signal from the immediately preceding unit circuit and one of a plurality of input parallel signals and shifts the selectiv... | 11/29/1983 |
| 4390970 | Rotating register utilizing field effect transistors A storage register which may be used to store several sets of data. The storage register may also be used as a demultiplexer to separate two or more sets of data that were received by the register over a single data line. The storage register includes a c... | 06/28/1983 |
| 4223233 | Charge transfer device input circuitry A charge transfer device having a source diffusion region, an isolation gate region, a reference voltage gate region and an input signal gate region disposed contiguously along such device, the isolation gate region being adapted for coupling to a pulse v... | 09/16/1980 |
| 4216391 | Circuit arrangement for generating a binary-coded pulse train A circuit arrangement for generating a pulse train having a predetermined first pulse spacing (a) and a second pulse spacing (b) differing from the first by an integral factor greater than one, which pulse spacings are assigned to the binary ZERO and the ... | 08/05/1980 |
| 4095093 | Synchronous state counter A synchronous state counter, which is responsive to an incrementing pulse for incrementing the state of the counter, is provided with a plurality of latches which output a binary representation of the number stored in the counter. Each latch is provided w... | 06/13/1978 |
| 4035662 | Capacitive means for controlling threshold voltages in insulated gate field effect transistor circuits Circuit means for eliminating the effect of excessive threshold voltages in insulated gate field effect transistor inverter-type circuits utilizes capacitor pull-up. Capacitors are selectively coupled from various phased voltage outputs of a multi-phase v... | 07/12/1977 |
| 4034238 | Field effect transistor information transfer circuit for use in storage register An output device of a metal-insulator-semiconductor transistor integrated circuit comprises, according to the invention, a penultimate stage, an output transistor, a clock pulse terminal and a separation pulse terminal. The penultimate stage incorporates ... | 07/05/1977 |
| 3992635 | N scale counter An n scale counter includes a shift register having X number of unit delay circuits connected in series and each consisting of a plurality of insulated gate field effect transistors. The unit delay circuits of the shift register are simultaneously supplie... | 11/16/1976 |
| 3976984 | Level shifting circuit device A level shifting circuit device comprises a first terminal connected to a high voltage power source, a P channel type IG-FET whose source and substrate electrodes are connected to said first terminal, means for applying a first pulse signal to the gate el... | 08/24/1976 |