Did You Know...
...that power steering was invented by independent inventor Francis W. Davis? As chief engineer in the 1920s of the truck division of the Pierce Arrow Motor Car Company, he saw how hard it was to steer heavy vehicles. So that he would be able to keep the profits from his future invention, Davis left his job, rented a small engineering shop in Waltham, Mass., and developed a hydraulic power steering system that led to power steering.
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| Number | Title | Issue Date |
| 7664219 | Flip-flop and shift register A flip-flop is provided. The flip-flop is used in a shift register in a source driver. The flip-flop is used to receive a first clock signal, an input signal and output an output signal. The output signal is fed back to the flip-flop. The flip-flop includes a flop c... | 02/16/2010 |
| 7430264 | Method to reduce transient current swings during mode transitions of high frequency/high power chips A method, an apparatus, and a computer program are provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances a... | 09/30/2008 |
| 7313212 | Shift register having low power consumption and method of operation thereof The shift register, which is an n-th shift register of a shift register chain, includes a first multiplexer, a second multiplexer, and a latch block, wherein n is a positive integer. The first multiplexer selects one of output data of the (n−1)-th shift register o... | 12/25/2007 |
| 7271618 | Multiple-time programming apparatus and method using one-time programming element A multiple-time programming apparatus and method using one-time programming (OTP) elements are provided. The apparatus comprises a first adjusting OTP element, a second adjusting OTP element and a logic device. An adjusting data is written into the first adjusting O... | 09/18/2007 |
| 7026849 | Reset circuit having synchronous and/or asynchronous modules There is provided a reset circuit for reducing current consumption during resetting. A reset circuit 20 is constituted in such a manner that a pulse generation circuit 22 for generating a reset pulse signal (PRSTN) 50 from a reset signal input t... | 04/11/2006 |
| 6907556 | Scanable R-S glitch latch for dynamic circuits A dynamic sequential device is provided that is adapted for scan control and observation. The dynamic sequential device may be scanned in-circuit as part of a scan chain in a VLSI device or it may be scanned as a discrete device. The dynamic sequential device mainta... | 06/14/2005 |
| 6759886 | Clock generating circuit generating a plurality of clock signals A clock generating circuit of a semiconductor integrated circuit device includes a plurality of stages of frequency-dividing circuits connected in series, of which a first stage receives a reference clock signal, each frequency-dividing circuit requiring no reset si... | 07/06/2004 |
| 6549605 | Limiting loss in a circuit A circuit for limiting loss in a second circuit. The circuit may include a first timer, a second timer and one or more logic gates. The first timer may produce a first output in a given state if the duration of a pulse for use with the second circuit reac... | 04/15/2003 |
| 6542569 | Memory device command buffer apparatus and method and memory devices and computer systems using same A command buffer for use in packetized DRAM includes a four stage shift register for shifting for sequentially storing four 10-bit command words. The shift register combines the four 10-bit command words into a single 40-bit command word and transfer the ... | 04/01/2003 |
| 6490332 | High speed, low-power shift register and circuits and methods using the same A shift register includes a plurality of shift register stages having inputs and outputs coupled to form a chain. Each stage includes enable and disable control inputs, with an output of a selected one of the stages coupled to the enable input of a stage ... | 12/03/2002 |
| 6396896 | Implementation of functions of multiple successive bits of a shift register A circuit for providing a function of a plurality of consecutive bits in a shift register is provided. The circuit includes a 2-input logic gate having a first input terminal connected to receive a bit being shifted into the shift register, and a second i... | 05/28/2002 |
| 6301322 | Balanced dual-edge triggered data bit shifting circuit and method A balanced dual-edge triggered bit shifting circuit includes a clock circuit to generate low skew, or edge-aligned, complementary clock signals, and a shift register that shifts a data bit in response to the complementary clock signals. The clock circuit ... | 10/09/2001 |
| 6201870 | Pseudorandom noise sequence generator A pseudorandom sequence generator including a first feedback shift register having at least one input and at least one output and a first controller having an output in communication with the at least one input of the first feedback shift register; the fi... | 03/13/2001 |
| 6088422 | One-pin shift register interface A register using a single pin to provide two or more control signals (e.g., clock and data signals). The present invention decodes a three state input waveform to generate a clock/write signal and uses a three state clock waveform to generate a clock/read... | 07/11/2000 |
| 6072849 | Shift counter device A programmable n stage shift counter divider circuit includes a plurality of n flip-flops arranged in cascade from a first stage to an nth stage. The data inputs of each of the flip flops are coupled with the output of the next preceding stage through cor... | 06/06/2000 |
| 6072873 | Digital video broadcasting In order to implement the Digital Video Broadcasting descrambling algorithm in the context of MPEG compressed data streams containing interleaved sections of scrambled and unscrambled data, at a data rate of 60 MBits/sec with a clock of 2.7 MHz, a stream ... | 06/06/2000 |
| 5995579 | Barrel shifter, circuit and method of manipulating a bit pattern The present invention provides for a circuit comprising: an input operable to receive a bit pattern; a bit-operator configured to selectively transpose the bit pattern; a shifter configured to shift the bit pattern following the transposition of the bit p... | 11/30/1999 |
| 5987090 | Method and apparatus for a logarithmic shift register A new class of shift registers that shift the contents of a 2n bit length register up to 2n -1 positions in n cycles. Shift registers according to the present invention can be constructed to shift left, shift right, or to shift eithe... | 11/16/1999 |
| 5881067 | Flip-flop design and technique for scan chain diagnosis A modification to conventional scan chain design is disclosed which can identify whether any connection in the scan chain is shorted to the supply voltage or ground (i.e., shorted to a logical 1 or logical 0) and the precise location of the short. Circuit... | 03/09/1999 |
| 5881121 | One-pin shift register interface A register using a single pin to provide two or more control signals (e.g., clock and data signals). The present invention decodes a three state input waveform to generate a clock/write signal and uses a three state clock waveform to generate a clock/read... | 03/09/1999 |
| 5790625 | Mechanism for enabling an array of numerous large high speed counters A large number of frequent events may be accurately counted by employing a shift register. The values of several bit positions within the shift register are logically combined to generate an input to the shift register. The input is shifted in to alter th... | 08/04/1998 |
| 5764718 | Ripple carry logic ASND method Apparatus and method to logically process signals representative of multiple bits of multiple-bit numbers include successively delaying application of the bit-representative signals to logical processing stages from associated input registers by a delay i... | 06/09/1998 |
| 5761265 | Parallel architecture for generating pseudo-random sequences A parallel architecture for implementing a digital sequence generator is provided, which contains taps connected to selected fixed memory cells and the taps of the logic circuitry are switched among the cells. The architecture disclosed and claimed herein... | 06/02/1998 |
| 5745541 | Data shift control circuit A data shift control circuit for a shift register in response to a logic operation command code is disclosed. The shift register includes a first register and a second register and the logic operation command code includes a first portion and a second por... | 04/28/1998 |
| 5742657 | Fast digital shift register and arrangement comprising such a register A digital shift register contains a succession of master-slave flipflops (M/S) which are controlled by a clock signal (H), and also comprises, at least between two master-slave flipflops (M/S), a switching device (C) which enables selection of a serial lo... | 04/21/1998 |
| 5706323 | Dynamic 1-of-2N logic encoding A system of encoding a plurality of logic paths. A number of logic paths are subdivided into groups of N, N being greater than one. Each group of N logic paths is encoded such that an assertion of a given combination of the N logic paths results in a pred... | 01/06/1998 |
| 5692026 | Apparatus for reducing capacitive loading of clock and shift signals by shifting register-based devices A shift register, circular pointer or ring counter presents a reduced capacitive load on the clock and shift signals used to control it. The device is constructed using one or more enhanced data cells. Each data cell has a data input, a data output, a clo... | 11/25/1997 |
| 5682340 | Low power consumption circuit and method of operation for implementing shifts and bit reversals The present invention describes a circuit (10) and associated method of operation for implementing bit reversals and shifts of an input data. The circuit (10) includes a plurality of input lines (12), a plurality of output lines (14), a plurality of shift... | 10/28/1997 |
| 5596617 | Feedback shift register for generating digital signals representing series of pseudo-random numbers A feedback shift register for generating digital signals representing pseudo-random number sequences has n-stages and exclusive OR-circuits in the feedback logic, as well as a clock-pulse generator. To be able to generate digital signals, which are well s... | 01/21/1997 |
| 5506796 | Digital signal processing circuit selectively operable in either a normal or a pseudorandom noise generative mode A circuitry with a pseudorandom noise generative function has a shift register for converting serial data into parallel data, an exclusive OR gate electrically connected to the shift register for fetching outputs from the shift register, the exclusive OR ... | 04/09/1996 |
| 5502408 | Circuit for decoding 2T encoded binary signals A decoding circuit for 2T encoded binary signals, comprises: a data input terminal; a first D-type flip flop having an input coupled to the input terminal; a first exclusive OR gate having inputs coupled to the input terminal and an output of the first D-... | 03/26/1996 |
| 5488318 | Multifunction register A multifunction data storage register is provided having at least one first register cell having a first input multiplexer for selecting between two input signals responsive to one or more control signals and having a first output signal, a first input ex... | 01/30/1996 |
| 5483566 | Method and apparatus for modifying the contents of a register via a command bit A method and apparatus as provided that simplifies the software required for modifying the contents of a register. By adding one gate to the register, a single command can be written to the register to modify the states of multiple bits. The system reduce... | 01/09/1996 |
| 5467037 | Reset generation circuit to reset self resetting CMOS circuits A self resetting CMOS (SRCMOS) circuit operates with a variable clock cycle. Circuit oscillation is avoided in either long or short clock cycles. At the same time, the circuit eliminates overlapping currents by incorporating a ground interrupt device. The... | 11/14/1995 |
| 5430336 | Emitter coupled logic circuit A emitter coupled logic circuit is reduced in circuit scale, while maintaining the speed of shift registers and compatibility with analog circuits. When data held in the first self-holding circuit section 41 or the second self-holding section 42 is delete... | 07/04/1995 |
| 5386390 | Semiconductor memory with looped shift registers as row and column drivers Address pointers (11, 12, 13, 14) include flip-flop circuits and flip-flop circuits including data through circuits. A control circuit (10) controls the flip-flop circuits such that the data through circuits of unnecessary flip-flop circuits cause data to... | 01/31/1995 |
| 5363424 | Partially-operable driver circuit A driver circuit comprising an output level selection circuit and a shift register is disclosed. The output level selection circuit has driving terminals, potential level input terminals and data input terminals, and an output signal having one of the dif... | 11/08/1994 |
| 5359636 | Register control circuit for initialization of registers A register control circuit has a plurality of registers, a control circuit for producing clock signals, and a logic circuit for producing latch clocks based on a reset signal and the clock signals. A shift data is inputted to a first one of the plurality ... | 10/25/1994 |
| 5355027 | Shift register circuit with three-input nor gates in selector circuit A shift register circuit includes a first two-input NOR circuit to which a first data signal and a selection signal are input, a second two-input NOR circuit to which a first reverse data signal having an opposite phase from the first data signal and the ... | 10/11/1994 |
| 5247215 | Frequency range detector A phase lock loop operates independent of temperature and process variation by digitally loading a VCO until reaching the desired operating frequency. The VCO reaches a high output frequency even under worst case processing by controlling multiple current... | 09/21/1993 |
