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| Number | Title | Issue Date |
| 8023612 | Shift register with dynamic entry point particularly useful for aligning skewed data Disclosed are, inter alia, methods, apparatus, computer-storage media, mechanisms, and means associated with a shift register with a dynamic entry point, which may particularly useful for aligning skewed data. The dynamic entry shift register typically includes a se... | 09/20/2011 |
| 7697656 | Shift register, method of controlling the same, electro-optical device, and electronic apparatus It is provided a method of controlling a shift register in which a plurality of transfer unit circuits, each having a storage unit and a writing unit, are connected in series. The storage unit has a hold gate and stores a logical level of a pulse when the hold gate ... | 04/13/2010 |
| 7430268 | Dynamic shift register with built-in disable circuit A disable circuit for using in a dynamic shift register unit comprising: a first input, a second input, an output, a first reference line for receiving a first supply voltage, a second reference line for receiving a second supply voltage, and six transistors. The di... | 09/30/2008 |
| 7373572 | System pulse latch and shadow pulse latch coupled to output joining circuit In one embodiment, an apparatus includes a system pulse latch to generate at least one system latch signal in response to a data input signal and a pulsed system clock signal; a shadow pulse latch to generate at least one shadow latch signal in response to the data ... | 05/13/2008 |
| 7342846 | Address decoding systems and methods Systems and methods provide improved address decoding techniques for memory. For example, in accordance with an embodiment of the present invention, an integrated circuit includes an address register that receives a reset signal, a clock signal, and an address signa... | 03/11/2008 |
| 7321506 | Multivibrator protected against current or voltage spikes The multivibrator is protected against current or voltage spikes and includes a first data transfer port that receives, as input, multivibrator input data, and a first/master latch cell connected on the output side of the first transfer port. A second/slave latch ce... | 01/22/2008 |
| 7319736 | Real-time digital x-ray imaging apparatus An x-ray diagnostic apparatus and methods performs Real-Time Digital Radiography with particular application in dental x-ray imaging modalities, such as Orthopantomography, Scannography, Linear Tomography and Cephalography, by using a versatile and modular electroni... | 01/15/2008 |
| 7313212 | Shift register having low power consumption and method of operation thereof The shift register, which is an n-th shift register of a shift register chain, includes a first multiplexer, a second multiplexer, and a latch block, wherein n is a positive integer. The first multiplexer selects one of output data of the (n−1)-th shift register o... | 12/25/2007 |
| 7278074 | System and shadow circuits with output joining circuit In one embodiment, an apparatus includes a system circuit adapted to generate at a first output terminal a first output signal in response to a data input signal and at least one system clock signal; a shadow circuit adapted to generate at a second output terminal a... | 10/02/2007 |
| 7230986 | Multistandard video decoder and decompression system for processing encoded bit streams including a video formatter and methods relating thereto A pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bit strea... | 06/12/2007 |
| 7221197 | Driver circuit of display device In a driver circuit of a display device, an electric potential difference between high-level power supply voltage VDD and low-level power supply voltage VSS2 in shift registers and buffers is set smaller than an electric potential difference between high-level volta... | 05/22/2007 |
| 7190342 | Shift register and display apparatus using same In a shift register, which is for use in an image display apparatus of the TFT active matrix type in which a driver circuit is integrally provided on a display panel, and which is so arranged as to boost a start pulse SP to a start pulse SPO by using a level shifter... | 03/13/2007 |
| 7164302 | One gate delay output noise insensitive latch A one gate delay output noise insensitive latch includes an input node, an output node, a storage node, a not storage node, and a data clock line. A primary latch element is connected to the input node, the output node, and the data clock line. A mirror primary latc... | 01/16/2007 |
| 7149811 | Multistandard video decoder and decompression system for processing encoded bit streams including a reconfigurable processing stage and methods relating thereto A pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bit strea... | 12/12/2006 |
| 7142626 | Apparatus and method of controlling multi-input-single-output systems An apparatus and method is disclosed for automatically controlling multi-input-single-output (MISO) systems or processes. The control output signal of a single-input-single-output (SISO) automatic controller is converted by a reverse, sequential or combined split-ra... | 11/28/2006 |
| 7126408 | Method and apparatus for receiving high-speed signals with low latency An apparatus and method for receiving high-speed signals having a wide common-mode range with low input-to-output latency. In one embodiment, the receiver includes an integrator to accumulate charge in accordance with an input signal during an integration time inter... | 10/24/2006 |
| 7095783 | Multistandard video decoder and decompression system for processing encoded bit streams including start codes and methods relating thereto A pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bit strea... | 08/22/2006 |
| 7038494 | Scan chain element and associated method A scan chain element in an integrated circuit, the scan chain element including; a first latch connected to accept test data as an input, a second latch connected to accept the output of the first latch as an input, control logic for accepting a clock signal and a h... | 05/02/2006 |
| 6999984 | Modification to reconfigurable functional unit in a reconfigurable chip to perform linear feedback shift register function A reconfigurable chip using reconfigurable functional units is modified to better implement linear feedback shift registers. The reconfigurable functional unit has its input multiplexer unit modified so that it can select a combined value. The combined values includ... | 02/14/2006 |
| 6975131 | Integrated module having a delay element Integrated module having a circuit and a plurality of input/output terminals, each of the input/output terminals being connected to a driver circuit for driving output signals and to a reception circuit for receiving input signals, a first delay element with a first... | 12/13/2005 |
| 6968486 | Master-slave-type scanning flip-flop circuit for high-speed operation with reduced load capacity of clock controller A master-slave-type scanning flip-flop circuit is capable of operating at a higher speed by reducing a load capacity of a clock controller. The master-slave-type scanning flip-flop circuit is used to test a semiconductor integrated circuit device, and has a master l... | 11/22/2005 |
| 6965262 | Method and apparatus for receiving high speed signals with low latency An apparatus and method for receiving high-speed signals having a wide common-mode range with low input-to-output latency. In one embodiment, the receiver includes an integrator to accumulate charge in accordance with an input signal during an integration time inter... | 11/15/2005 |
| 6964003 | Integrated circuit testing system and method A system and method for testing the data propagation time in an integrated circuit at relatively low speed is described herein. The method uses at least two parallel circuits comprising a data circuit and a clock circuit, wherein these parallel circuits are provided... | 11/08/2005 |
| 6950930 | Multistandard video decoder and decompression system for processing encoded bit streams including pipeline processing and methods relating thereto A pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bit strea... | 09/27/2005 |
| 6944810 | Method and apparatus for the testing of input/output drivers of a circuit In order to test the input and output drivers of a circuit, in particular an integrated semiconductor circuit, a method and apparatus is provided to connect the input or output drivers assigned to individual signal connections of the circuit to be tested in series t... | 09/13/2005 |
| 6940300 | Integrated circuits for testing an active matrix display array A device for use in a display system including an array of pixel cells formed on a substrate. Each pixel cell being coupled to at least one gate line of a plurality of gate lines formed on the substrate and at least one data line of a plurality of data lines being f... | 09/06/2005 |
| 6938225 | Scan design for double-edge-triggered flip-flops A double-edge-triggered flip-flop scan cell. The double-edge-triggered flip-flop scan cell provides the capability to capture and output data for each edge of a clock signal in a functional mode of a host integrated circuit. In a test mode, the double-edge triggered... | 08/30/2005 |
| 6930522 | Method and apparatus to delay signal latching A first circuit is to generate a data signal containing data. A second circuit is to utilize said data, where the first and second circuits are commonly clocked by a latch signal, further a circuit has a first level sensitive latch to latch the data signal from the ... | 08/16/2005 |
| 6919740 | MOLECULAR-JUNCTION-NANOWIRE-CROSSBAR-BASED INVERTER, LATCH, AND FLIP-FLOP CIRCUITS, AND MORE COMPLEX CIRCUITS COMPOSED, IN PART, FROM MOLECULAR-JUNCTION-NANOWIRE-CROSSBAR-BASED INVERTER, LATCH, AND FLIP-FLOP CIRCUITS Methods for implementing familiar electronic circuits at nanoscale sizes using molecular-junction-nanowire crossbars, and nanoscale electronic circuits produced by the methods. In one embodiment of the present invention, a 3-state inverter is implemented. In a secon... | 07/19/2005 |
| 6910125 | Multistandard video decoder and decompression system for processing encoded bit streams including a decoder with token generator and methods relating thereto A pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bit strea... | 06/21/2005 |
| 6845274 | Communication port control module for lighting systems An improved technique of interfacing a computer lighting device to a control computer is disclosed, wherein a hardware device is interposed between the control computer and the lighting device. The hardware device handles certain functions in hardware, thereby permi... | 01/18/2005 |
| 6778626 | Bi-directional shift-register circuit A bi-directional shift-register circuit for outputting data in different turns according to a switching signal. Each shift-register unit includes a first input terminal, a second input terminal, an output terminal and a clock input terminal for receiving the clock s... | 08/17/2004 |
| 6611248 | Shift register and electronic apparatus Each of stages RS(1), RS(2), . . . of a shift register is constituted by six TFTs. A ratio of a channel width and a channel length (W/L) of each of these TFTs 1 to 6 is set in accordance with a transistor characteristic of each TFT in such a manner that t... | 08/26/2003 |
| 6556647 | Phase locked loop clock divider utilizing a high speed programmable linear feedback shift register with a two stage pipeline feedback path An apparatus and method is disclosed for providing a phase locked loop clock divider circuit utilizing a high speed linear feedback shift register with a two stage pipeline in its feedback path. A plurality of "pre-load" flip flop (PLFF) circuits and mult... | 04/29/2003 |
| 6339631 | Shift register A shift register that is suitable for reducing the required number of clock signals as well as simplifying the configuration of an external control circuit uses a plurality of stages connected, in series, to a start pulse input line. In each stage, an out... | 01/15/2002 |
| 6324239 | Method and apparatus for a 1 of 4 shifter The present invention comprises a multi-function shifter that uses N-nary logic and includes an operation selection and various 1-of-N multiplexers to support a variety of shift modes. The shift modes include rotates, logical shifts in which 0 is shifted ... | 11/27/2001 |
| 5818894 | High speed barrel shifter A high speed barrel shifter in which fill input data is especially added. The high speed barrel shifter comprises: a first multiplexer having a first and a second input terminals for receiving double word and input data, thereby producing fill data at a f... | 10/06/1998 |
| 5790066 | Remote control transmission circuit A remote control transmission circuit for generating a multicarrier under control of a single microcomputer. This transmission circuit is arranged so as to allow reduction of the number of the program commands and making it easy to perform a different pro... | 08/04/1998 |
| 5761266 | Shifter circuit that emulates a barrel shifter A shifting circuit operates on a plurality of input sub-words, that collectively constitute an input data word, to generate a plurality of result sub-words that collectively represent the input data word, shifted. The shifting circuit receives, during eac... | 06/02/1998 |
| 5745541 | Data shift control circuit A data shift control circuit for a shift register in response to a logic operation command code is disclosed. The shift register includes a first register and a second register and the logic operation command code includes a first portion and a second por... | 04/28/1998 |
