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| Number | Title | Issue Date |
| 8175216 | Shift register circuit A shift register circuit is provided that can decrease a power consumption caused by a clock signal and can achieve a high driving capacity. A unit shift register has a first transistor that activates an output signal when a power supply potential is provided to an ... | 05/08/2012 |
| 7889832 | Bootstrap circuit, shift register employing the same and display device Disclosed is a shift register which includes first transistor connected between a first clock signal terminal and an output terminal, a second transistor with a gate connected to an input terminal and a source connected to a gate of the first transistor, a third tra... | 02/15/2011 |
| 7443944 | Shift register, image display apparatus containing the same and signal generation circuit A unit shift register includes a first transistor for supplying an output terminal with a clock signal, and second and third transistors for discharging the output terminal, and further includes a fourth transistor having its gate connected to the gate node of the s... | 10/28/2008 |
| 7406147 | Shift register A shift register includes multiple stages connected with each other in succession. The shift register stores the threshold voltage of an amorphous silicon thin-film transistor in a capacitor. During operation, the bias applied to the transistor is adjusted according... | 07/29/2008 |
| 7317780 | Shift register circuit A shift registers circuit having a series of cascading shift registers comprises a first transistor coupling to an output signal of a pre-stage shift register, a second transistor coupling to the first transistor, an output and a first clock signal, and a pull-down ... | 01/08/2008 |
| 7274313 | High speed data recording with input duty cycle distortion Data from both a positive edge sample and negative edge sample are used to determine a data bit. The primary and secondary clocks capture two copies of the data. A sample is taken with a positive edge of one clock and the negative edge of the other clock each bit pe... | 09/25/2007 |
| 7184013 | Semiconductor circuit in which power consumption is reduced and semiconductor circuit system using the same A semiconductor circuit system includes a first signal line and n circuit sections (n is an integer equal to or more than 2), each of which has an input terminal and an output terminal. The input terminals of predetermined k ones (k is an integer satisfying 2≦k | 02/27/2007 |
| 7177182 | Rewriteable electronic fuses Rewriteable electronic fuses include latches and/or logic gates coupled to one or more nonvolatile memory elements. The nonvolatile memory elements are configured to be programmed to memory values capable of causing associated electronic circuits to settle to predet... | 02/13/2007 |
| 7174014 | Method and system for performing permutations with bit permutation instructions The present invention provides permutation instructions usable in a programmable processor for solving permutation problems in cryptography, multimedia and other applications. PPERM and PPERM3R instructions are defined to perform permutations by a sequence of... | 02/06/2007 |
| 7145370 | High-voltage switches in single-well CMOS processes Circuits are provided for high-voltage switching in single-well CMOS processes. ... | 12/05/2006 |
| 7123300 | Image processor and method of processing images An image processor arranged in operation to generate an interpolated video signal from a received video signal representative of an image. The image processor comprises an adaptable register store comprising a plurality of register elements and is coupled to a contr... | 10/17/2006 |
| 7120855 | Survivor path memory circuit and Viterbi decoder with the same A survivor path memory circuit and a Viterbi decoder with the circuit for saving the memory amounts. The Viterbi decoder includes a branch metric generator, an ACS (Add-Compare-Select) unit, a survivor path memory circuit and a decoding unit. The survivor path memor... | 10/10/2006 |
| 7061975 | Noncyclic digital filter and radio reception apparatus comprising the filter In accordance with the invention, in a nonrecursive digital filter, the number of times each bit of input data passes through a shift register is reduced to save power. Despreading data is sent to a first shift register and a second shift register, each having a num... | 06/13/2006 |
| 7027550 | Shift register unit and signal driving circuit using the same A shift register unit. The shift register unit outputs a shift register signal according to a clock signal, an inverse clock signal and a start signal. The shift register has first and second clock inversion circuits, and an inverter. In the first clock inversion ci... | 04/11/2006 |
| 6972747 | Method for compensating a perturbed capacitive circuit and application to matrix display device A process for compensating a circuit including at least one first conductor with a specified potential, at least one second conductor generating disturbances on the first conductor by capacitive coupling, and a first bus with a reference voltage, coupled capacitivel... | 12/06/2005 |
| 6970116 | Multiplexer circuit for converting parallel data into serial data at high speed and synchronizing the serial data with a clock signal A multiplexer circuit converts parallel data into serial data synchronized with an internal clock signal, and the multiplexer circuit has a logic circuit, a load circuit, and a plurality of switching elements. The logic circuit processes the internal clock signal an... | 11/29/2005 |
| 6967639 | Image display device, scan line drive circuit and driver circuit for display device An image display device, a scan line drive circuit and a driver circuit for the display device capable of driving the display device having a multiplex pixel structure by simple control and utilizing a simplified gate driver. The image display device includes a plur... | 11/22/2005 |
| 6785389 | System for bitstream generation A bitstream generator including a plurality of linear feed shift registers (LFSRs) operative to generate a bit stream and including: at least a first LFSR operative, when assigned as a generator during a first time period including at least one clock cycle, to provi... | 08/31/2004 |
| 6381690 | Processor for performing subword permutations and combinations An apparatus for operating on the contents of an input register to generate the contents of an output register which contains a permutation, with or without repetitions, or a combination of the contents of the input register. The apparatus partitions the ... | 04/30/2002 |
| 6295046 | Shift register unit and display device A shift register unit has stages. In each stage, a clamping transistor and the control electrode of an output transistor are connected to the output electrode of an input transistor to which an output one stage behind is input. A pull-down resistor is con... | 09/25/2001 |
| 6108394 | Single cell per bit shift register A shift register matrix including a matrix of cells having a plurality of rows and a plurality of columns, each cell storing one bit of data. A plurality of pulse generators is included to generate pulses to the cells which cause new data to be shifted in... | 08/22/2000 |
| 6064713 | Shift register using "MIS" transistors of like polarity A shift register having several cascaded stages, each stage containing an output at a first node connected to a next stage, a first input connected to an output of a preceding stage, a second input connected to an output of the next stage and a first term... | 05/16/2000 |
| 5912937 | CMOS flip-flop having non-volatile storage A flip-flop includes non-volatile storage of a bit for encryption purposes or other applications. The non-volatile bit remains in the flip-flop, substantially unaltered, irrespective of normal flip-flop operation, and is available to be recalled whenever ... | 06/15/1999 |
| 5790066 | Remote control transmission circuit A remote control transmission circuit for generating a multicarrier under control of a single microcomputer. This transmission circuit is arranged so as to allow reduction of the number of the program commands and making it easy to perform a different pro... | 08/04/1998 |
| 5778037 | Method for the resetting of a shift register and associated register A method for the resetting of a group of series-connected non-transparent synchronous memory cells. The method includes modifying the clock signals that control the transfer gates of these cells on the activation of a resetting signal to set all the trans... | 07/07/1998 |
| 5771268 | High speed rotator with array method A high-speed rotator array for shifting input data a specified amount. The rotator array includes a plurality of straight shift control lines extending across the array for receiving shift data representative of shift values, and a plurality of input term... | 06/23/1998 |
| 5652718 | Barrel shifter A barrel shifter performs multi-bit shift and rotate operations on data of different lengths using multiplexors to preprocess the data prior to introducing the data to a transistor array.... | 07/29/1997 |
| 5481749 | Shift register divided into a number of cells and a number of stages within each cell to permit bit and multiple bit shifting An array processing system has a plurality of processing elements, each of which includes a processor and an associated memory module, and a router network over which each processing element can transfer messages to other random processing elements. The s... | 01/02/1996 |
| 5381455 | Interleaved shift register An interleaved shift register 20 includes a plurality of data storage elements 22a-22d having a common data input signal. Each of the plurality of data storage elements 22a-22d has an enable control input that is connected to one of a plurality of clock s... | 01/10/1995 |
| 5339079 | Digital-to-analog converter with a flexible data interface A flexible data interface (21, 22) for a digital-to-analog converter (25, 26) includes a mute circuit (46, 70, 71 ) to mute and de-mute input data in 6 dB steps over a time period such as one-quarter of a second. The mute circuit includes a counter (46) t... | 08/16/1994 |
| 5321733 | Counter circuit using Johnson-type counter and applied circuit including the same A counter circuit includes Johnson-type counters of m stages, each counter including a plurality of flip-flops connected in a cascade connection, each flip-flop receiving a clock signal at a respective clock input end. In the constitution, signals at resp... | 06/14/1994 |
| 5268949 | Circuit for generating M-sequence pseudo-random pattern The present invention provides a MRP generator comprising m MRP generating circuits connected in parallel which are operated at a 1/m clock speed and have a predetermined time relation to each other, wherein the MRP generating circuits are operated on the... | 12/07/1993 |
| 5198999 | Serial input/output semiconductor memory including an output data latch circuit A semiconductor memory has an output data latch circuit controlled in response to a clock signal shifted by a half period from a control clock input to n one-bit shift register stages. The memory device includes a plurality of read data latch circuits, as... | 03/30/1993 |
| 5150389 | Shift register The input nodes and output nodes of a plurality of storing circuits for storing plural-bit data are connected to one another to constitute a shift register. Each of the plurality of storing circuits includes a selection circuit for selecting 1-bit data fr... | 09/22/1992 |
| 5126758 | Optical printer An optical printer with a print head having numerous light emitting elements for reproducing medium densities of a multi-tone document image faithfully. When image data are inputted to individual serial shift registers, the entry of next image data is inh... | 06/30/1992 |
| 5090036 | Two-phase-clocked shift register is bipolar technology A shift register is disclosed in which an n-stage shift-register chain (sr) consists of 2n series-connected, like basic cells (zi) which are driven in antiphase by a first and a second shift clock (C1, C2) from a clock generator (g). The nonoverlap range ... | 02/18/1992 |
| 4951302 | Charge-coupled device shift register A two phase shift register comprises four serial registers each having an input section, a transfer section, and a lead-in section disposed between the input section and the transfer section. The input sections provide respective sequences of charge sampl... | 08/21/1990 |
| 4903285 | Efficiency shift register An improved shift register uses fewer than 2*N latches, where N is the capacity in bits of the shift register and also the propagation delay from the input to the output of the shift register in terms of the system clock. An m-phase set of clocks are used... | 02/20/1990 |
| 4879718 | Scan data path coupling Apparatus is disclosed for forming scan data path subchains from the elemental memory units of a digital system, and interconnecting the scan data path subchains to form an extended serial shift register for scan testing. The method and apparatus for form... | 11/07/1989 |
| 4873665 | Dual storage cell memory including data transfer circuits A dual storage cell memory includes an array of dual storage cells, each of the dual storage cells containing a first memory cell and a second memory cell. The first and second memory cells are well known six-transistor static memory cells with the additi... | 10/10/1989 |
