Did You Know...
...that several people are credited with the invention of the flush toilet? Most people have heard of Thomas Crapper (1837-1910), the sanitary engineer who invented the valve-and-siphon arrangement that made the modern toilet possible. Another claimant to "the throne" was British inventor Alexander Cumming who patented a toilet in 1775. Then there's a nameless Minoan (a native of ancient Crete) who lived 4,000 years ago who supposedly was ahead of his time and created the first flush toilet!
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| Number | Title | Issue Date |
| 7889831 | N-bit shift register controller A column repair circuit uses a system of circuits that automatically stops the shifting of register contents independently of the number of bits to be shifted. The circuit is only dependent on the number of bits in a column address repair block. By adding shift regi... | 02/15/2011 |
| 7555094 | Counter capable of holding and outputting a count value and phase locked loop having the counter Example embodiments may provide a counter capable of outputting a count value after holding the count value for an amount of time and a phase locked loop (PLL) including the counter. The counter may include a selection unit that may selectively output a clock signal... | 06/30/2009 |
| 7430264 | Method to reduce transient current swings during mode transitions of high frequency/high power chips A method, an apparatus, and a computer program are provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances a... | 09/30/2008 |
| 7352602 | Configurable inputs and outputs for memory stacking system and method Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications. More specifically, embodiments of the present invention include memory devices that include a die having a circuit configured for enablemen... | 04/01/2008 |
| 7353371 | Circuit to extract nonadjacent bits from data packets A method and device to copy data fields from one or more source packets to one or more result packets. In a SET function, adjacent data fields in a source packet is copied to respective destination data fields in a result packet governed by a field locator packet. I... | 04/01/2008 |
| 7350058 | Shift and insert instruction for overwriting a subset of data within a register with a shifted result of another register A data processing system 2 is provided which supports shift-and-insert instructions SLI, SRI which serve to shift a source data value by a specified shift amount and then insert bits from that shifted value other than the shifted-in bits into a destination va... | 03/25/2008 |
| 7349519 | Shift register without noise and liquid crystal display device having the same A shift register structure comprising a shift register for sequentially outputting voltages as a clock signal and a start voltage are inputted thereto, and a cleaner means connected to the shift register for removing noise within the start voltage. The cleaner means... | 03/25/2008 |
| 7345701 | Line buffer and method of providing line data for color interpolation A line buffer and a method of providing data to a 3×3 line interpolation processor using the line buffer in an image processing system, such as a digital camera, includes a readable and writable single memory, a buffer register having a prior data area storing firs... | 03/18/2008 |
| 7342568 | Shift register circuit A shift register circuit having shift registers comprising a first transistor having a gate and a first source/drain for receiving an output signal of a pre-stage shift register, a second transistor having a gate coupled to a second source/drain of the first transis... | 03/11/2008 |
| 7313212 | Shift register having low power consumption and method of operation thereof The shift register, which is an n-th shift register of a shift register chain, includes a first multiplexer, a second multiplexer, and a latch block, wherein n is a positive integer. The first multiplexer selects one of output data of the (n−1)-th shift register o... | 12/25/2007 |
| 7289594 | Shift registrer and driving method thereof A shift register having a plurality of stages for shifting a start pulse and outputting a shifted start pulse to a next stage, each of the plurality of stages includes a pull-up transistor controlled by a first node to apply a first clock signal to an output line, a... | 10/30/2007 |
| 7265581 | Level shifter The level shifter comprises a coupling block, a PMOS switch, a first PMOS transistor and a second PMOS transistor. The coupling block receives a first signal and a second signal to generate a first control signal and a first reference voltage. The first signal and t... | 09/04/2007 |
| 7256618 | Semiconductor integrated circuit device A semiconductor integrated circuit device (1) includes: a transistor switch (SWA) for electrically connecting and disconnecting output of a flip-flop (FF64) of a shift register (SR1) and input of a flip-flop (FF65) of a shift register (SR... | 08/14/2007 |
| 7203265 | Synchronous counting circuit A M by N bit synchronous counter for use in advanced applications is provided. The M by N bit synchronous counter comprises an M by N register configured to receive and store data corresponding to at least one word integrated with a N bit counter configured to seque... | 04/10/2007 |
| 7202728 | Signal transmission circuit The signal transmission circuit comprises a first switch controls output according to a first control pulse, the first source follower outputting signals to the first output line based on signal input into the gate, a first capacitor connected between the gate and t... | 04/10/2007 |
| 7174014 | Method and system for performing permutations with bit permutation instructions The present invention provides permutation instructions usable in a programmable processor for solving permutation problems in cryptography, multimedia and other applications. PPERM and PPERM3R instructions are defined to perform permutations by a sequence of... | 02/06/2007 |
| 7154321 | Digital delay line A digital delay line including a first feedback delay line having a first number of interlinked first delay elements, at least one second feedback counter having a second number of second interlinked counting elements, the counting elements being clocked by one of t... | 12/26/2006 |
| 7134035 | Method for generating a synchronization signal based on the clock ratio between two clock domains for data transfer between the domains A method for communicating across first and second frequency domains of an integrated microchip is provided. The method initiates with determining a clock ratio between the first frequency domain and the second frequency domain. The first frequency domain is associa... | 11/07/2006 |
| 7119582 | Phase detection in a sync pulse generator A phase detector and phase detection method for a sync pulse generator operable in a clock synchronizer that effectuates data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain. The first clock do... | 10/10/2006 |
| 7096358 | Encrypting file system An encryption method that is largely transparent to a user is accomplished by intercepting a change document or open document command, carrying out an encryption or decryption process, and then completing the command on an encrypted or decrypted file. The encryption... | 08/22/2006 |
| 7081890 | Bi-directional driving circuit of flat panel display device and method for driving the same A bi-directional driving circuit of a flat panel display device and method for driving the same is disclosed in the present invention. The bi-directional driving circuit of a flat panel display device having a plurality of blocks driven by a start pulse Vst, first t... | 07/25/2006 |
| 7042973 | Variable dividing circuit To provide a variable dividing circuit having a high operational speed. The variable dividing circuit includes a shift register configured by cascade connection of D-type flip-flops (D11, D12, . . . , D1n) with an initializing means by clock syn... | 05/09/2006 |
| 7027550 | Shift register unit and signal driving circuit using the same A shift register unit. The shift register unit outputs a shift register signal according to a clock signal, an inverse clock signal and a start signal. The shift register has first and second clock inversion circuits, and an inverter. In the first clock inversion ci... | 04/11/2006 |
| 7026849 | Reset circuit having synchronous and/or asynchronous modules There is provided a reset circuit for reducing current consumption during resetting. A reset circuit 20 is constituted in such a manner that a pulse generation circuit 22 for generating a reset pulse signal (PRSTN) 50 from a reset signal input t... | 04/11/2006 |
| 7024579 | Configurable timing system having a plurality of timing units interconnected via software programmable registers The timing system includes a plurality of timing units interconnected to perform a count operation. Software programmable registers interconnect the plurality of timing units, and a control circuit generates a clock signal for the plurality of timing units. The cont... | 04/04/2006 |
| 6996203 | Bidirectional shift register and display device incorporating same The present invention includes: a shift register section, including multiple-stage flip-flops operating in synchronism with a clock signal, for switching a shift direction in accordance with an externally supplied direction instruct signal; a waveform change section... | 02/07/2006 |
| 6996737 | System and method for delayed increment of a counter A method and structure for performing a delayed counter increment is provided. The method and structure allows a counter decision to be modified based upon what the computer system hardware does with the data packet. Subsequent to the generation of a counter command... | 02/07/2006 |
| 6985993 | Control register assembly A control register assembly controls components to be controlled in an electric circuit. The control register assembly includes a control register. The control register is formed by at least one shift register, whose elements are distributed over the electric circui... | 01/10/2006 |
| 6967639 | Image display device, scan line drive circuit and driver circuit for display device An image display device, a scan line drive circuit and a driver circuit for the display device capable of driving the display device having a multiplex pixel structure by simple control and utilizing a simplified gate driver. The image display device includes a plur... | 11/22/2005 |
| 6919794 | Circuit for controlling the random character of a random number generator A circuit for controlling the random character of a bit flow, including an input shift register receiving the bit flow and having its outputs exploited in parallel, at least one element for comparing at least a partial content of the input register with predetermine... | 07/19/2005 |
| 6898261 | Method and apparatus for monitoring event occurrences Method and apparatus for monitoring event occurrences, e.g., from an event signal, where a register and a counter are employed. In one embodiment, the register is designed to have a capture bit for capturing the occurrence of a monitored event. The shifting of the s... | 05/24/2005 |
| 6857043 | Shift register implementations of first-in/first-out memories utilizing a double increment gray code counter First-in/first-out (“FIFO”) memory circuitry includes first and second Gray-code-based counters for respectively counting write and read clock signals. A Gray code subtractor subtracts from one another the counts output by the counters. Shift register circuitry ... | 02/15/2005 |
| 6845274 | Communication port control module for lighting systems An improved technique of interfacing a computer lighting device to a control computer is disclosed, wherein a hardware device is interposed between the control computer and the lighting device. The hardware device handles certain functions in hardware, thereby permi... | 01/18/2005 |
| 6839397 | Circuit configuration for generating control signals for testing high-frequency synchronous digital circuits A circuit configuration for generating control signals for testing high-frequency synchronous digital circuits, especially memory chips, is described. A p-stage shift register which is clocked at a clock frequency corresponding to the high clock frequency of the dig... | 01/04/2005 |
| 6785389 | System for bitstream generation A bitstream generator including a plurality of linear feed shift registers (LFSRs) operative to generate a bit stream and including: at least a first LFSR operative, when assigned as a generator during a first time period including at least one clock cycle, to provi... | 08/31/2004 |
| 6728330 | Register arrangement for a microcomputer with a register and further storage media There is provided a register system of a microcomputer having a register that includes at least one register bit and having an additional storage arrangement allocated to the register and on which the data content of the register is able to be intermediately stored.... | 04/27/2004 |
| 6683932 | Single-event upset immune frequency divider circuit A single-event upset immune frequency divider circuit is disclosed. The single-event upset immune frequency divider circuit includes a dual-path shift register, a dual-path multiplexor, and a summing circuit. The dual-path shift register has a clock input... | 01/27/2004 |
| 6654439 | High speed linear feedback shift register An apparatus and method for providing a high speed linear feedback shift register is disclosed. The high speed linear feedback shift register of the present invention comprises multiplexer flip flop circuits. The multiplexer gate on the input of each flip... | 11/25/2003 |
| 6621886 | Shift register having fewer lines therein, and liquid crystal display having the same A shift register has m stages which store one of two states, where m is an integer more than 1, each stage including clock input terminals at which n-phase clock signals are input, where n is an integer more than 1, and an input terminal, and an output te... | 09/16/2003 |
| 6556646 | Shift register A shift register for driving a pixel row in a liquid crystal display device. In the shift register, a plurality of stages are connected to a high level voltage source, a low level voltage source and a phase-delayed clock signal generator, connected to row... | 04/29/2003 |
