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| Number | Title | Issue Date |
| 7343510 | Method and device for selecting one of multiple clock signals based on frequency differences of such clock signals A clock detection and selection circuit (100) can include a first counter (102-0) that generates a first count value CNT1 according to a first clock signal CLK1 and a second counter (102-1) that generates a second cou... | 03/11/2008 |
| 7269397 | Method and apparatus for measuring communications link quality A method and apparatus for measuring communications link quality provides accurate on-chip estimation of the difficulty of achieving a particular bit error rate (BER) for a communications link. A low cost/complexity accumulator circuit connected to internal signals ... | 09/11/2007 |
| 7260731 | Saving power when in or transitioning to a static mode of a processor A method for reducing power utilized by a processor including the steps of determining that a processor is transitioning from a computing mode to a mode is which system clock to the processor is disabled, and reducing core voltage to the processor to a value suffici... | 08/21/2007 |
| 7230495 | Phase-locked loop circuits with reduced lock time PLL circuits are provided in which a voltage-controlled oscillator (VCO) comprising one or more voltage-controlled delay units (VCDs) is initialized with the control voltage of a voltage-controlled delay line (VCDL) having substantially identical VCDs. In general, V... | 06/12/2007 |
| 7219676 | Substrate detecting apparatus A substrate cleaning apparatus includes a bath in the form of a vessel filled with a cleaning liquid, a substrate guide disposed on the bottom of the vessel and configured to support at least one substrate vertically, a first sensing unit for sensing the substrate(s... | 05/22/2007 |
| 7212045 | Double frequency signal generator A double frequency signal generator to which a synchronization signal having a duty cycle of 1% to 999% is inputted. The synchronization signal is used for triggering of a switching component at positive and negative edges to generate a triangular-wave signal. An av... | 05/01/2007 |
| 7212054 | DLL with adjustable phase shift using processed control signal Circuits and methods are described for producing a DLL clock signal with adjustable phase shift using a processed control signal. In one embodiment of the invention, a DLL circuit is provided that includes a main and smaller variable delay circuits, a phase detector... | 05/01/2007 |
| 7196554 | Integrated clock supply chip for a memory module, memory module comprising the integrated clock supply chip, and method for operating the memory module under test conditions An integrated chip has a clock signal input (1.1) for application of a first clock signal (clk1) and a clock signal output (1.2–1.5). Moreover, it has a phase locked loop (2), which, on the input side, is connected to the clock signal i... | 03/27/2007 |
| 7190755 | Phase-locked loop circuitry for programmable logic devices A phase-locked loop circuit (“PLL”) is adjustable in both phase and frequency. By providing a plurality of taps on the voltage-controlled oscillator of the PLL, and providing separate multiplexers, each of which can select a different tap—one for the PLL feedb... | 03/13/2007 |
| 7178135 | Scope-based breakpoint selection and operation Methods, apparatus and articles of manufacture, performed by a debugging program, for executing an operation on a plurality of breakpoints within a scope. In one aspect, the method comprises selecting the scope; determining the plurality of breakpoints within the sc... | 02/13/2007 |
| 7161884 | Information disc recording/playback apparatus and method for counting pulses and controlling a rotation speed of an information disc The present invention provides an information disc recording/playback apparatus which includes a track cross detection means, a track cross direction detection means, a rotation angle detection means, and a count means, detects the track pitch of a disc, evaluates t... | 01/09/2007 |
| 7149956 | Converging error-recovery for multi-bit-incrementing gray code An L-bit gray-code input value can change by more N bits at a time. The lower N bits of the input are stored as a received least-significant-bits (LSB) while the upper bits are stored as a received most-significant-bits (MSB). A stored register holds the corrected, ... | 12/12/2006 |
| 7134042 | Frequency detection circuit and data processing apparatus A frequency detection circuit according to the present invention has a status holding register for storing rise information and fall information about a check target clock and outputting an error detection signal showing frequency abnormality when information showin... | 11/07/2006 |
| 7133654 | Method and apparatus for measuring communications link quality A method and apparatus for measuring communications link quality provides accurate on-chip estimation of the difficulty of achieving a particular bit error rate (BER) for a communications link. A low cost/complexity accumulator circuit connected to internal signals ... | 11/07/2006 |
| 7104624 | Fire pulses in a fluid ejection device An fluid ejection device includes nozzles and includes firing resistors which correspond to the nozzles. Each firing resistor and corresponding nozzle are located in zones on the fluid ejection device where each zone has at least one firing resistor and correspondin... | 09/12/2006 |
| 7098279 | Non-flammable and non-combustible adhesive bonding systems having adherence to low energy surfaces This invention relates to (meth)acrylate based polymerizable compositions and adhesive systems prepared therefrom, which include an initiator system comprising a complex of an organoborane with a complexing agent, an aziridine-containing compound, and a carrier mate... | 08/29/2006 |
| 7095254 | Method for producing a control signal which indicates a frequency error A method which provides a very simple way of forming a control signal if the frequencies differ too greatly from one another between a useful signal and a reference signal. A control signal is produced which indicates that the frequency error between the frequencies... | 08/22/2006 |
| 7091760 | DLL with adjustable phase shift using processed control signal Circuits and methods are described for producing a DLL clock signal with adjustable phase shift using a processed control signal. In one embodiment of the invention, a DLL circuit is provided that includes a main and smaller variable delay circuits, a phase detector... | 08/15/2006 |
| 7088154 | Methods and arrangements for a low power phase-locked loop Methods and arrangements for a low power, phase-locked loop (PLL) are disclosed. Embodiments include a multi-phase oscillator like a voltage-controlled oscillator (VCO) to generate multiple phases of a clock signal. The multiple phases are then combined to generate ... | 08/08/2006 |
| 7079428 | Circuit for distribution of an input signal to one or more time positions A control circuit and memory including the control circuit are described herein. The control circuit provides for controlling the edge gradient of transmission signals which are produced by transmission drivers in an integrated circuit, with each transmission signal... | 07/18/2006 |
| 7075365 | Configurable clock network for programmable logic device In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmenta... | 07/11/2006 |
| 7071743 | Programmable phase-locked loop circuitry for programmable logic device A phase-locked loop (“PLL”) for use in a programmable logic device (“PLD”) is constructed with modular components, which may be digital, and which may be programmable or adjustable, in place of the conventional analog charge pump and loop filter. Connections... | 07/04/2006 |
| 7069425 | Real-time processor executing predetermined operation defined by program correctly at predetermined time A real-time processor includes a clock register updating a time at a predetermined interval, a time register storing an arbitrary time, a time comparator comparing the time in the clock register with the time stored in the time register, and an instruction processin... | 06/27/2006 |
| 7049864 | Apparatus and method for high frequency state machine divider with low power consumption A digital frequency divider apparatus includes a plurality of next-state generator elements receiving an input clock signal thereto, and configured to generate a next value for each of a corresponding plurality of internal state variables. A plurality of flip-flop e... | 05/23/2006 |
| 7047519 | Dynamic setting of breakpoint count attributes Apparatus, methods and articles of manufacture are provided for tracking breakpoint hits. In one embodiment, a hit count is automatically incremented for each breakpoint. The hit count is stored for subsequent runs, thereby allowing a user to specify a breakpoint en... | 05/16/2006 |
| 7035799 | Method and device for voice recognition A method and a device are set forth which make it possible to set an accuracy in a voice recognition process. To this end, system parameters of the voice recognition system are determined using an input quantity via a mapping specification, and the voice recognition... | 04/25/2006 |
| 7035365 | Error correction method and apparatus for data transmission system A receiver involved in high-speed data transmission includes a decision system. The decision system calculates a value of an input signal and holds the value as a tentative value. The decision system calculates an error value, amplifies the error value, and holds th... | 04/25/2006 |
| 7029084 | Integrated programmable fire pulse generator for inkjet printhead assembly An inkjet printhead assembly includes at least one inkjet printhead having nozzles and firing resisters. The inkjet printhead assembly includes fire pulse generator circuitry responsive to a start fire signal to generate fire signals, each having a series of fire pu... | 04/18/2006 |
| 7027499 | Detection and correction circuit for blind equalization convergence errors An apparatus processes an equalizer output signal. The equalizer output signal is formed by transmitting an alternate mark inversion input signal over a channel and passing the transmitted signal through an adaptive equalizer. The apparatus includes a correlator cir... | 04/11/2006 |
| 7024551 | Method and apparatus for updating boot code using a system controller Method and apparatus are disclosed that allow boot code within the apparatus to be updated using a system controller. The apparatus includes a central processing unit (CPU) and a programmable memory that contains boot code at a predetermined location for use in boot... | 04/04/2006 |
| 7019570 | Dual-gain loop circuitry for programmable logic device A loop circuit (PLL or DLL) uses a dual-gain voltage-controlled component (VCO or VCDL) to achieve a phase (and frequency) lock with reduced jitter. A coarse control feedback path includes a detector for achieving an approximate lock. This path operates over a wide ... | 03/28/2006 |
| 7009437 | Smart buffer circuit to match a delay over a range of loads A clock duty cycle correction circuit. The duty cycle correction circuit is provided at a receiver in a clock distribution network to correct a duty cycle of a distributed clock signal. ... | 03/07/2006 |
| 6975696 | Built-in self test for a counter system A self test for a counter system in an integrated circuit includes a clock coupled to counters in a plurality of counters. A first counter in the plurality of counters has a first counter output and a first counter rollover. A second counter in the plurality of coun... | 12/13/2005 |
| 6965272 | Worldwide marketing logistics network including strategically located centers for frequency programming crystal oscillators to customer specification A worldwide logistics network includes a processing center for receiving customer orders for crystal oscillators over communications links, processing the orders, and generating work orders that are selectively disseminated over communications links to programming c... | 11/15/2005 |
| 6959062 | Variable delay line A variable delay line includes a shift register responsive to coarse adjustment control and a fine adjustment control. The variable delay line can be used in a delay lock loop within an integrated circuit. The variable delay line receives coarse and fine adjustment ... | 10/25/2005 |
| 6954113 | Programmable oscillator circuit A programmable crystal oscillator is provided having a memory for storing frequency-defining parameters. Typically, one of these parameters is used to program an adjustable capacitive load circuit coupled to a crystal to thereby adjust the crystal source frequency. ... | 10/11/2005 |
| 6939932 | Initiator systems, polymerisable compositions, and uses thereof for bonding low surface energy substrates Use of an initiator system comprising: a combination of an organoborane and a polyaziridine, in a ratio of aziridine groups to boron atoms of greater than 1.3:1, as an initiator of polymerisation in an ad... | 09/06/2005 |
| 6934595 | Method and system for reducing semiconductor wafer breakage In a system and method to reduce wafer breakages in a wafer handling system, the position of a wafer on a platen is monitored and closing of the platen on a vacuum chamber is prevented if a misaligned wafer is detected. In one embodiment the wafer position is monito... | 08/23/2005 |
| 6924678 | Programmable phase-locked loop circuitry for programmable logic device A phase-locked loop (“PLL”) for use in a programmable logic device (“PLD”) is constructed with modular components, which may be digital, and which may be programmable or adjustable, in place of the conventional analog charge pump and loop filter. Connections... | 08/02/2005 |
| 6911843 | Data transfer device for transferring data between blocks of different clock domains The number of pulses of a clock signal CLK-A is circularly counted in a count range from “0” to “7”, and count signals indicating count values are produced. A clock signal CLK-B having a frequency lower than that of the clock signal CLK-A is produced from co... | 06/28/2005 |
