Mouse device with a built-in printer
A mouse device for use as an input device of a computer is provided that includes a housing in which recording paper is loadable, and a printer unit provided within the housing for printing on the recording paper print information received from the computer.
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| Number | Title | Issue Date |
| 7991104 | Modular low power gray code counter A modular Gray code counter of arbitrary bit length having identical Gray code counter cells in every bit position. Each cell comprises a Toggle Flop and logic which triggers the Toggle Flop and sets the state of the Gray code counter cell. The two outputs of a cell... | 08/02/2011 |
| 7596201 | Gray code counter and display device therewith There is offered a Gray code counter with which a delay time of a critical path is reduced and a fast operation is made possible. A first Gray code bit Q0 is obtained by outputting an output signal Q0o of an RDFF 2 through an RDFF 31 | 09/29/2009 |
| 7526059 | Balanced Grey code utilization to increase NVM endurance A counting device includes a set of memory cells, including multiple groups of the memory cells configured to store count words of a count code, which include a less significant word and a more significant word. A controller assigns first and second groups of the me... | 04/28/2009 |
| 7366274 | Bidirectional shift register A bidirectional shift register includes a former stage multiplexer, a latter stage multiplexer, a former stage full-swing shift register, and a latter stage full-swing shift register, all of which have a plurality of registers all of the same type. The former and th... | 04/29/2008 |
| 7242329 | Method and system for prioritizing data values for robust data representation Methods, systems and data structures select prioritized robust data values from a plurality of available data values formed by a plurality of data bits, each capable of exhibiting a bit value. Available data values are arranged into a gray code format, and alternate... | 07/10/2007 |
| 7194500 | Scalable gray code counter The invention is a Gray code counter that uses a carry chain to determine the state of each bit of the counter. An additional bit that toggles at every clock is used to originate the carry chain, and to determine the counter direction. Then, a generic Gray count bit... | 03/20/2007 |
| 7149275 | Integrated circuit and method of implementing a counter in an integrated circuit An integrated circuit, such as a programmable logic device, implements a single bit transition counter in logic. The counter preferably comprises a first stage receiving a clock signal having a first clock rate and generating a least significant bit in a count. A pl... | 12/12/2006 |
| 7148825 | Data interface including gray coding A data interface includes a network interface processor, a transmitter, and a receiver. The network interface processor is operably coupled to transceive parallel data via a network connection. The transmitter is operably coupled to convert outbound parallel data fr... | 12/12/2006 |
| 7149956 | Converging error-recovery for multi-bit-incrementing gray code An L-bit gray-code input value can change by more N bits at a time. The lower N bits of the input are stored as a received least-significant-bits (LSB) while the upper bits are stored as a received most-significant-bits (MSB). A stored register holds the corrected, ... | 12/12/2006 |
| 7092480 | High-speed synchronous counters with reduced logic complexity Described are fast synchronous counters with reduced combinatorial logic. In one embodiment, a four-bit shift register is configured in a ring and preset with a data pattern (e.g., 1000). The register is then rapidly shifted into any of four unique states. Combinato... | 08/15/2006 |
| 7085341 | Counter with non-uniform digit base A nonvolatile counter. A nonvolatile storage is organized in digits having non-uniform bases. Circuitry is provided to increment a count value represented by the digits in response to an increment command. ... | 08/01/2006 |
| 7075352 | Latch-based pulse generator There is provided a pulse generator capable of generating a pulse with a reduced number of transistors that toggle in response to a clock signal, thereby reducing power consumption. The pulse generator includes a plurality of unit cells, wherein an nth unit cell (n ... | 07/11/2006 |
| 7071855 | Gray code conversion method and apparatus embodying the same A generalized Gray code converter includes a decimal-binary to intermediate-binary converter and an intermediate-binary to Gray code converter. The decimal-binary to intermediate-binary converter is operable to convert a sequence of sets of electrical signals encode... | 07/04/2006 |
| 6950138 | Gray code counter Conventionally, it is difficult to design the logic of a Gray code counter that can be used in interlaced counting. Even though interlaced counting is possible with a Gray code counter, the number of simultaneously changing bits increases greatly depending on the nu... | 09/27/2005 |
| 6937172 | Method and system for gray-coding counting A system for gray-code counting in an integrated circuit such as a programmable logic device uses a binary adder coupled to a binary counter output and to a selected binary offset value. The binary adder provides a binary sum that is converted to a gray code value b... | 08/30/2005 |
| 6937688 | State machine, counter and related method for gating redundant triggering clocks according to initial state A state machine, a counter, and related method for gating redundant triggering clocks according to the initial states is provided. The state machine includes a plurality of state units and a clock gating circuit. Each of the state unit is triggered by a clock to gen... | 08/30/2005 |
| 6931091 | Gray code counter A gray code is produced from a minimum of gate logic by making available and monitoring master outputs of master-slave latch pairs, where the latch pairs are arranged to form a cascading chain of toggle flip-flop stages. The least significant bit through one less th... | 08/16/2005 |
| 6907098 | Gray code counter A Gray code counter includes a holding circuit, first and second conversin circuit and an operation circuit. The holding circuit stores gray code signals and outputs the stored gray code signals in response to a clock signal. The first conversion circuit receives th... | 06/14/2005 |
| 6900745 | Method of scalable gray coding A method for generating a modulo Gray-code representation of a non-power-of-two set of binary values begins by determining a desired Gray-code sequence length. The method then continues by determining a bus width, M, in bits, based on the desired Gray-code sequence ... | 05/31/2005 |
| 6879654 | Non-integer frequency divider circuit A non-integer frequency divider is disclosed. The non-integer frequency divider circuit includes several base stages connected to each other. The non-integer frequency divider circuit also includes a clocking circuit for passing an enable bit from one of the base st... | 04/12/2005 |
| 6857043 | Shift register implementations of first-in/first-out memories utilizing a double increment gray code counter First-in/first-out (“FIFO”) memory circuitry includes first and second Gray-code-based counters for respectively counting write and read clock signals. A Gray code subtractor subtracts from one another the counts output by the counters. Shift register circuitry ... | 02/15/2005 |
| 6845414 | Apparatus and method of asynchronous FIFO control An apparatus and method for controlling an asynchronous First-In-First-Out (FIFO) memory. The asynchronous FIFO has separate, free running read and write clocks. A number of n-bit circular Gray code counters are used to handshake the operation between read and write... | 01/18/2005 |
| 6836525 | Method for establishing a gray code and related counter circuit A method for establishing a Gray code count sequence having N code words includes determining a first bit switch sequence having 2M−1 elements and a bit switching sequence property according to a first Gray code count sequence having 2M code ... | 12/28/2004 |
| 6792065 | Method for counting beyond endurance limitations of non-volatile memories A digital counter that uses non-volatile memories as storage cells, wherein the storage cells are sub-divided into two groups, one for the implementation of a rotary counter that keeps track of the less significant part of the count and a binary counter that keeps t... | 09/14/2004 |
| 6762701 | Scalable gray code counter and applications thereof A non-power-of-two modulo N Gray-code counter (the “Gray-code counter”) and a binary incrementer-decrementer algorithm are disclosed. One embodiment of the Gray-code counter of this invention comprises a Gray-to-binary converter for receiving an M-bit Gray-code ... | 07/13/2004 |
| 6735270 | Asynchronous up-down counter and method for operating the same An asynchronous up-down counter includes a plurality of counter blocks. Each of the counter blocks has a counter output, an up-down control output, and an up-down control input. A counter signal output from each of the counter blocks has at least two bits. The async... | 05/11/2004 |
| 6707874 | Multiple-output counters for analog-to-digital and digital-to-analog conversion A machine used for digital counting which can provide multiple output counts. The machine is particularly useful in analog-to-digital (A/D) converters and in digital-to-analog (D/A) converters. The multiple output counts can change in different directions or in the ... | 03/16/2004 |
| 6703950 | Gray code sequences The present invention comprises a method of Gray encoding/decoding of binary and Gray code sequences that are less than full-length, resulting in a geometrically reduced storage requirement.... | 03/09/2004 |
| 6687325 | Counter with non-uniform digit base A nonvolatile counter. A nonvolatile storage is organized in digits having non-uniform bases. Circuitry is provided to increment a count value represented by the digits in response to an increment command.... | 02/03/2004 |
| 6639963 | Up/down gray code counter and solid-state image sensor provided with such a counter A conventional up/down Gray code counter has both a logic circuit section for up counting and a logic circuit section for down counting, and thus has a large circuit scale. To overcome this inconvenience, an up/down Gray code counter of the invention has ... | 10/28/2003 |
| 6473484 | Binary counter and method for counting to extend lifetime of storage cells A digital counter and method for counting are implemented which minimize fatigue-related failure in the storage element for the count value. The counting sequence is chosen such that the transitions within individual storage elements are the same for each... | 10/29/2002 |
| 6434642 | FIFO memory system and method with improved determination of full and empty conditions and amount of data stored A structure and method for operating an asynchronous first in, first out (FIFO) memory system in which the full or empty condition of the memory is determined by comparing a currently-generated write address with a currently-generated read address and a n... | 08/13/2002 |
| 6337893 | Non-power-of-two grey-code counter system having binary incrementer with counts distributed with bilateral symmetry A gray-code counter system (AP1) for a RAM-based FIFO comprises a read pointer (10), a write pointer (20), and a detector (30). The read pointer includes a gray-code decoder (11), a binary incrementer (12), a gray-code encoder (13), and a register (14) that ho... | 01/08/2002 |
| 6314154 | Non-power-of-two Gray-code counter and binary incrementer therefor Non-power-of-two Gray-code counters, including modulos 10, 12, 14, and 22 are disclosed, along with a sequencing method they employ. Each counter includes a register for storing an N-bit, e.g., 4-bit, Gray-code count. The count is converted to binary code... | 11/06/2001 |
| 6269138 | Low power counters A low power counter for cycling through a predetermined sequence of states in response to pulses on an input line includes a number of counter blocks, corresponding to the number of bits of the counter, connected in series. The low power counter blocks in... | 07/31/2001 |
| 6249562 | Method and system for implementing a digit counter optimized for flash memory A system and method of implementing a digit counter having a plurality of digits, ranging from a least significant digit (LSD) to a maximum positional digit (MDP), is described. In one embodiment, the system comprises switching a single digit for each inc... | 06/19/2001 |
| 6084935 | Binary counter and method for counting to extend lifetime of storage cells A digital counter and method for counting are implemented which minimize fatigue-related failure in the storage element for the count value. The counting sequence is chosen such that the transitions within individual storage elements are the same for each... | 07/04/2000 |
| 6075833 | Method and apparatus for counting signal transitions A circuit for counting events occurring between two different clock domains includes a gray code counter having at least two stages. The gray code counter is incremented by the event to be counted. Dual rank synchronizer circuit and delay flip/flops are c... | 06/13/2000 |
| 5923718 | Binary counter reading circuit An asynchronous reading circuit improves reliability of data read from a binary counter. Count data generated by a binary counter 101 according to a counting clock is converted into a gray code by a gray encoder. The count data represented by the gray cod... | 07/13/1999 |
| 5778415 | Apparatus, systems and methods for controlling electronic memories Memory control circuitry is provided which includes circuitry for generating a sequence of gray code values. Counter circuitry is coupled to the gray code circuitry and controls the duration of assertion of each of the generated gray code values. Bus circ... | 07/07/1998 |