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A self defense weapon formed as a memo pad and which is easily held by a person's fingers, therefore making it possible to provide protection from a mugger and also to quickly and easily write a record or a message without failure of missing or forgetting significant information under a stressful situation.
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| Number | Title | Issue Date |
| 7372248 | Electronic circuit, system with an electronic circuit and method for testing an electronic circuit An electronic circuit having an input, an output with an input filter for delaying a change of an input signal and a control component for supplying an output signal and evaluating the input signal. The delay is a time constant. An industrial automation system is pr... | 05/13/2008 |
| 7292177 | Counter circuit, AD conversion method, AD converter, semiconductor device for detecting distribution of physical quantities, and electronic apparatus An asynchronous counter that is capable of switching count mode includes flip-flops, and three-input single-output tri-value switches respectively provided between the adjacent pairs of the flip-flops. The tri-value switches switch among three values, namely, non-in... | 11/06/2007 |
| 7262648 | Two-latch clocked-LSSD flip-flop A clocked level-sensitive scan design may have flip-flops designed to have data, scan-in, and output ports and to utilize two clock signals. Such a clocked level-sensitive scan flip-flop may be built utilizing two latches. ... | 08/28/2007 |
| 7251766 | Test method and test circuit for electronic device A method of testing an electronic device including first and second semiconductor devices connected to each other with a plurality of bus lines. First, the first semiconductor device supplies a selected one of the bus lines with a first logical output signal. Then, ... | 07/31/2007 |
| 7243036 | System and method for calibrating the clock frequency of a clock generator unit over a data line In order to further develop a system (100) and a method for calibrating the clock frequency of at least one clock generator unit (38), in particular oscillator unit, that is assigned to at least one transmitting/receiving module (30), wherein—... | 07/10/2007 |
| 7197104 | Minimum gate delay edge counter An edge counter counting both rising and falling edges of an input signal is implemented with combinational logic, without using flip-flops. The combinational logic is designed using intermediate signals and state transitions producing an output signal having a cycl... | 03/27/2007 |
| 7133017 | Shift register and display device using same A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn−1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between a... | 11/07/2006 |
| 6992937 | Column redundancy for digital multilevel nonvolatile memory A digital multilevel bit memory array system comprises regular memory arrays and redundant memory arrays. A regular y-driver corresponds to each memory array to read or write contents to a multilevel bit memory cell and compare the read cell content to reference vol... | 01/31/2006 |
| 6975696 | Built-in self test for a counter system A self test for a counter system in an integrated circuit includes a clock coupled to counters in a plurality of counters. A first counter in the plurality of counters has a first counter output and a first counter rollover. A second counter in the plurality of coun... | 12/13/2005 |
| 6962817 | Reference control for optical measurement of nucleated red blood cells of a blood sample Reference control compositions and the method of use are disclosed for measurement of nucleated red blood cells, which includes one set of synthetic spherical particles having a mean particle diameter ranging from 6.2 μm to 6.8 μm and a refractive index from 1.58 ... | 11/08/2005 |
| 6950490 | Fault state detection mechanism for a ring-counter-based frequency divider-by-N that generates non-overlapping N-phases of divide-by-N clocks with 1/N duty ratio A fault state detector for a ring counter is formed from unit current sources each switched under the control of a different one of the outputs of the ring counter. The currents switched in that manner are passed through a unit resistance to generate a voltage signa... | 09/27/2005 |
| 6947077 | Fast and accurate adjustment of gain and exposure time for image sensors A proportional counting circuit generates count values for use in variably adjusting gain and exposure time of an image sensor array. The count values are adjusted in proportion to the current count value. This technique allows for fast and accurate adjustment of ga... | 09/20/2005 |
| 6944737 | Memory modules and methods having a buffer clock that operates at different clock frequencies according to the operating mode Memory modules and methods of testing memory modules are provided that include at least one memory device responsive to a memory clock signal having a memory clock frequency and a data buffer. The data buffer is responsive to a buffer clock signal having a first buf... | 09/13/2005 |
| 6937688 | State machine, counter and related method for gating redundant triggering clocks according to initial state A state machine, a counter, and related method for gating redundant triggering clocks according to the initial states is provided. The state machine includes a plurality of state units and a clock gating circuit. Each of the state unit is triggered by a clock to gen... | 08/30/2005 |
| 6876939 | Method and device of carrier wave frequency calibration for remote controller The present invention discloses wave frequency calibration method and device for remote controller, the device of the present invention comprises an oscillator for generating a base wave; a storage for storing a match value; a modifier for generating a modified sign... | 04/05/2005 |
| 6853698 | Ripple counter circuits and methods providing improved self-testing functionality A ripple counter circuit supports two modes of operation, a user mode and a test mode. In the user mode, the circuit functions as a standard ripple counter, counting in response to first edges (e.g., rising edges) on a clock input signal. In the test mode, the rippl... | 02/08/2005 |
| 6828817 | Testing device included in the electrooptic device The invention provides an electrooptic device and an electronic apparatus, in which the electrical characteristics of many thin-film switching elements formed in a substrate to support an electrooptic material can be accurately inspected. The invention also provides... | 12/07/2004 |
| 6823275 | Fault tolerant apparatus and method for determining a revolution rate of a gear An apparatus comprises an edge detector, a memory and a pulse-input engine. The edge detector is configured to receive an input signal and a counter signal. The edge detector is further configured to send a set of time values based on the input signal and the counte... | 11/23/2004 |
| 6711513 | Fault tolerant apparatus and method for determining a revolution rate of a gear A measurement system and method for determining a revolution rate of a rotating gear is described. Such a rotating gear can be, for example, a turbine or compressor. The described measurement system and method, for example, can perform highly accurate measurements a... | 03/23/2004 |
| 6266625 | Calibrating high resolution measurements There is described a method and system for calibrating measurements, in particular for calibrating a high resolution counter against an accurate real time calibrated clock signal. The method comprising obtaining the calibrated low resolution clock measure... | 07/24/2001 |
| 6031887 | High-speed binary synchronous counter An integrated circuit includes an n-bit counter having a plurality of k subcounters where both n and k are integers. At least one of the subcounters includes a switchable device adapted to receive a carry-out signal from an adjacent subcounter as a first ... | 02/29/2000 |
| 5960052 | Low power scannable counter A low power scannable asynchronous counter which is fully testable and which consumes low power in a functional mode consists of counter cells cascaded through NOR gate circuits to which clock signals are applied for each of the stages or cells. Each of t... | 09/28/1999 |
| 5877657 | PLL clock generator having trimmable frequency dividers A reference clock signal oscillator generates a reference clock signal. A first programmable counter performs frequency dividing on the reference clock signal and outputs a reference signal resulting-from the frequency dividing. A voltage controlled oscil... | 03/02/1999 |
| 5740219 | Digital counter test circuit A system for testing a digital counter of mn stages, in which the counter is organized into m segments, each of n bits, includes a two input exclusive OR gate connected between each of the m segments. One of the two inputs of each exclusive OR gate is obt... | 04/14/1998 |
| 5651040 | Dynamic division system and method for improving testability of a counter A method and system for testing a digital counter of mn bits comprises dividing the counter into m segments, each of n bits. For test purposes, the counter then is further divided into first and second m segment groups. Multiplex gates are used between th... | 07/22/1997 |
| 5526390 | Decoded counter with error check and self-correction A decoded counter employing a shift register and a zero-detect circuit has the ability of returning to a correct state within a limited number of clock cycles if an invalid state is accidentally assumed by the counter. One of the flip-flops is provided wi... | 06/11/1996 |
| 5526392 | Method of scaling the outputs of a binary counter A method and circuit for selectively scaling a binary counter having N serially connected stages in which an output count from the counter is 2M times the number of clock signals that have been input to the counter. The first M stages of the co... | 06/11/1996 |
| 5481580 | Method and apparatus for testing long counters An n-bit counter (18) (where n is an integerࣙ1) may be tested by first reconfiguring the counter during a test mode to generate successive first and second half-counts when the counter is successively clocked. During the test mode, a logical equality co... | 01/02/1996 |
| 5479412 | Apparatus for testing counter circuit In an apparatus for testing a counter circuit, a test pattern is used to drive the counter circuit to obtain an output pattern. The output pattern is compared with an expected pattern in synchronization with the test pattern, thereby determining whether o... | 12/26/1995 |
| 5473651 | Method and apparatus for testing large embedded counters An N stage counter includes peripheral circuitry for testing the operability of the counter. The peripheral circuitry includes gating means coupled between certain stages of the counter for partitioning the counter into at least first and second counter s... | 12/05/1995 |
| 5402458 | Mechanism to accelerate counter testing without loss of fault coverage Test circuitry for a counter of n number of bits is described. The circuitry includes that which divides the counter into s number of segments when the counter is being tested in a test mode. The invention also includes circuitry for detecting when each s... | 03/28/1995 |
| 5381453 | Efficient functional test scheme incorporated in a programmable duration binary counter A new technique for testing the counting functionality, loading functionality, and operational speed of a binary counter is provided wherein additional logic is incorporated into the counter to enable the counter to be functionally tested with a minimum n... | 01/10/1995 |
| 5371773 | Driving circuit for solid-state image sensor and counter circuit used therein A counter circuit includes counting stages of n bits where n is a natural number. The counter circuit also includes a logic decoding circuit for determining the inputs of the counting stages, a logic circuit for adjusting the number of simultaneous change... | 12/06/1994 |
| 5339343 | Counter circuit with or gates interconnecting stages to provide alternate testing of odd and even stages during test mode A counter circuit includes a plurality of one-bit counters connected in series. The counter circuit includes first and second input terminals which are supplied with a predetermined signal, respectively, in an operational test mode. The counter circuit fu... | 08/16/1994 |
| 5333162 | High resolution time interval counter A high resolution counter circuit measures the time interval between the occurrence of an initial and a subsequent electrical pulse to two nanoseconds resolution using an eight megahertz clock. The circuit includes a main counter for receiving electrical ... | 07/26/1994 |
| 5225768 | Field test instrument A calibration generator for furnishing signals to tachographs, taximeters and other instruments used in fleet management systems. Calibrated frequencies and amplitudes are provided by the generator of the invention. A PLL controlled synthesizer, driven by... | 07/06/1993 |
| 5185769 | Easily testable high speed digital counter A high speed digital counter that can be easily tested comprises a plurality of subcounters having an input for receiving an incrementing signal and a carry output for outputting a carry signal when the subcounter has reached its counting capacity. The ca... | 02/09/1993 |
| 5150036 | Process and apparatus for calibrating a particle counter A process and apparatus for calibrating a particle counter is described. The process comprises the steps of forming a vector gas flow by an aerosol of particles of the same grain size, developing ions in the vector gas with both sign by a bipolar charger,... | 09/22/1992 |
| 4991185 | Method of testing n-bit programmable counters This invention relates to a method of testing an n-bit programmable counter. It is desired to test the n-bit programmable counter in fewer than 2n cycles. Accordingly, a counter value output on the counter is coupled to a variable increment rat... | 02/05/1991 |
| 4989222 | Electronic hubodometer A hubodometer (10) for attachment to a vehicle's wheel structure for sensing a rotation of the wheel structure and for converting the sensed rotation to a distance travelled. The hubodometer comprises an outer housing (12) having a permanent magnet (28) a... | 01/29/1991 |
