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| Number | Title | Issue Date |
| 8064567 | Method and device for the incremention of counter statuses stored in memory cells of a memory A method for the incrementation of counter statuses in memory cells, which are arranged respectively in rows and columns of a first memory adds a “1” to the memory content of a memory cell of a second memory, which corresponds to the memory cell at the start of ... | 11/22/2011 |
| 8027425 | Asynchronous loadable down counter The disclosed embodiments relate to an asynchronous down counter, which can be loaded with any value N and then decrement exactly N times. The counter comprises an array of cells, wherein each cell is configured to hold a digit in a redundant base-k representation o... | 09/27/2011 |
| 7782995 | Low latency counter event indication A hybrid counter array device for counting events with interrupt indication includes a first counter portion comprising N counter devices, each for counting signals representing event occurrences and providing a first count value representing lower order bits. An ov... | 08/24/2010 |
| 7688931 | Space and power efficient hybrid counters array A hybrid counter array device for counting events. The hybrid counter array includes a first counter portion comprising N counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count v... | 03/30/2010 |
| 7573969 | Counter using shift for enhanced endurance A counting device includes a set of memory cells, which are configured to store respective bits of a count code. A controller is coupled to the memory cells so as to increment, in response to occurrences of a count input, the count code in the set of the memory cell... | 08/11/2009 |
| 7551706 | Counter device and counting method A counter device includes: a rewritable counter having a non-volatile memory which requires sector erasure to once turn all data in a sector into high data, prior to changing low data into high data in respective bits; and a control section updating a counter value ... | 06/23/2009 |
| 7532700 | Space and power efficient hybrid counters array A hybrid counter array device for counting events. The hybrid counter array includes a first counter portion comprising N counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count v... | 05/12/2009 |
| 7437622 | Implementation-efficient multiple-counter value hardware performance counter An implementation-efficient, multiple-counter value hardware performance counter is disclosed. A hardware counter of one embodiment includes a memory array and a hardware incrementer. The array stores counter values that are indexable by an index constructed based a... | 10/14/2008 |
| 7426253 | Low latency counter event indication A hybrid counter array device for counting events with interrupt indication includes a first counter portion comprising N counter devices, each for counting signals representing event occurrences and providing a first count value representing lower order bits. An ov... | 09/16/2008 |
| 7369432 | Method for implementing a counter in a memory with increased memory efficiency A method for implementing a counter in memory, e.g., non-volatile memory such as flash memory. A first number of first binary values indicating a first portion of a current number of the counter in a binary field may be stored in a portion of memory. Storing the fir... | 05/06/2008 |
| 7352606 | Monotonic counter using memory cells A monotonous counter formed as an integrated circuit, each counting bit being provided by a memory cell containing at least one memorization element formed of a polysilicon resistor, programmable by irreversible decrease in its value. ... | 04/01/2008 |
| 7330481 | Highly channelized port polling in a telecommunications switch A method of telecommunication network switch port polling enables very highly channelized ports to be polled. A polling engine reads information from at least one of a plurality of poll registers, and each of the plurality of poll registers is associated with a uniq... | 02/12/2008 |
| 7286764 | Reconfigurable modulator-based optical add-and-drop multiplexer An optical add and drop multiplexer system comprising a first module for providing a first signal; a second module for providing a second signal; and a modulator for receiving a channel of the first signal at a first location, the first location configured to actuat... | 10/23/2007 |
| 7272754 | Implementation-efficient multiple-counter value hardware performance counter An implementation-efficient, multiple-counter value hardware performance counter is disclosed. A hardware counter of one embodiment includes a memory array and a hardware incrementer. The array stores counter values that are indexable by an index constructed based a... | 09/18/2007 |
| 7157953 | Circuit for and method of employing a clock signal The circuits and methods of the present invention relate to circuits for generating a multiplied clock signal based upon a reference clock signal, and circuits using the clock signal to deserialize data. According to one embodiment of the invention, a circuit compri... | 01/02/2007 |
| 7154983 | Method of operating a first-in first-out (FIFO) circuit The present invention provides an overflow detector for a FIFO. The FIFO includes a plurality of registers each having an input and an output, a plurality of write signals each respectively coupled to a clock, one of the plurality of registers, and a plurality of re... | 12/26/2006 |
| 7149275 | Integrated circuit and method of implementing a counter in an integrated circuit An integrated circuit, such as a programmable logic device, implements a single bit transition counter in logic. The counter preferably comprises a first stage receiving a clock signal having a first clock rate and generating a least significant bit in a count. A pl... | 12/12/2006 |
| 7148825 | Data interface including gray coding A data interface includes a network interface processor, a transmitter, and a receiver. The network interface processor is operably coupled to transceive parallel data via a network connection. The transmitter is operably coupled to convert outbound parallel data fr... | 12/12/2006 |
| 7120220 | Non-volatile counter A non-volatile counter circuit includes a state machine having a first input for receiving one or more control signals, a second input for receiving a current count value, a third input for receiving historical information, and an output for providing a next count v... | 10/10/2006 |
| 7120685 | Method and apparatus for dynamic configurable logging of activities in a distributed computing system A system and method for implementing tracking of computing system activities wherein the tracking can be dynamically adjusted. The system provides a multiple level logging system having a first level for detecting message level errors and a second trace level for ob... | 10/10/2006 |
| 7117079 | Apparatus and method for simultaneous monitoring, logging, and controlling of an industrial process An apparatus performs simultaneous data monitoring, logging, and controlling of the state of a system. The apparatus includes at least one system sensor that provides a sensor data signal corresponding to a system characteristic of which the sensor is detecting, a m... | 10/03/2006 |
| 7111110 | Versatile RAM for programmable logic device Circuits and methods for providing versatile RAM for a programmable logic device are provided. These circuits and methods preferably allow signal lines that may be used to provide inputs for logic elements to be used instead for addressing memory blocks that form th... | 09/19/2006 |
| 7093084 | Memory implementations of shift registers A random access memory array is used as a shift register. Data is written into different locations in a first column of the memory and then gradually transferred successively to any other number of columns in the memory. Such column-to-column data transfer is the re... | 08/15/2006 |
| 7085341 | Counter with non-uniform digit base A nonvolatile counter. A nonvolatile storage is organized in digits having non-uniform bases. Circuitry is provided to increment a count value represented by the digits in response to an increment command. ... | 08/01/2006 |
| 7073069 | Apparatus and method for a programmable security processor A digital logic circuit comprises a programmable logic device and a programmable security circuit. The programmable security circuit stores a set of authorized configuration security keys. The programmable security circuit compares the authorized configuration secur... | 07/04/2006 |
| 7068372 | MEMS interferometer-based reconfigurable optical add-and-drop multiplexor The interferometer comprises a beam splitter, a mirror and a phase modulator. The beam splitter splits a signal into a first portion and a second portion. The mirror reflects the first portion. The first portion includes an optical path length, which is fixed. The p... | 06/27/2006 |
| 7065607 | System and method for implementing a counter A counter is provided which can be implemented in flash memory allowing longer life through fewer erasures. The counter is incremented using a method that minimizes bit transitions from 1 to 0. In one embodiment, the counter is implemented in m+n bits. The bits of t... | 06/20/2006 |
| 7057819 | High contrast tilting ribbon blazed grating The light modulator includes elongated elements and a support structure coupled to the elongated elements. Each element includes one or more lengthwise slits within an active optical area, and a light reflective planar surface with the light reflective planar surfac... | 06/06/2006 |
| 7058839 | Cached-counter arrangement in which off-chip counters are updated from on-chip counters In a first aspect, a counter is maintained in main memory, and a corresponding counter having a smaller number of bits is maintained in cache memory. The counter in cache memory is incremented and when a certain count threshold is reached, the corresponding counter ... | 06/06/2006 |
| 7054515 | Diffractive light modulator-based dynamic equalizer with integrated spectral monitor An integrated device of the present invention comprises free-space optics, a bi-directional multiplexor/de-multiplexor, a diffractive light modulator, a beam splitter, an optical performance monitor, and a controller. The free-space optics collimate, transform and i... | 05/30/2006 |
| 7049164 | Microelectronic mechanical system and methods The current invention provides for encapsulated release structures, intermediates thereof and methods for their fabrication. The multi-layer structure has a capping layer, that preferably comprises silicon oxide and/or silicon nitride, and which is formed over an et... | 05/23/2006 |
| 7042611 | Pre-deflected bias ribbons A modulator for and a method of modulating an incident beam of light including means for supporting a plurality of active elements and a plurality of bias elements, each active and bias element including a light reflective planar surface with the light reflective pl... | 05/09/2006 |
| 7042973 | Variable dividing circuit To provide a variable dividing circuit having a high operational speed. The variable dividing circuit includes a shift register configured by cascade connection of D-type flip-flops (D11, D12, . . . , D1n) with an initializing means by clock syn... | 05/09/2006 |
| 7027202 | Silicon substrate as a light modulator sacrificial layer An optical MEM device is fabricated with a patterned device layer formed on a silicon wafer. Preferably, the patterned device layer is patterned with plurality of ribbons and/or access trenches. The central portion of the ribbon is released from the silicon wafer us... | 04/11/2006 |
| 7024579 | Configurable timing system having a plurality of timing units interconnected via software programmable registers The timing system includes a plurality of timing units interconnected to perform a count operation. Software programmable registers interconnect the plurality of timing units, and a control circuit generates a clock signal for the plurality of timing units. The cont... | 04/04/2006 |
| 7012950 | Apparatus for generating pseudo-noises code and method for generating pseudo-noise codes using the same An apparatus for generating pseudo-noise codes adapted for advancing or retarding pseudo-noise chips generated therefrom within one clock in a radio communication network based on code division multiple access (CDMA). The apparatus includes a control uni for outputt... | 03/14/2006 |
| 6999984 | Modification to reconfigurable functional unit in a reconfigurable chip to perform linear feedback shift register function A reconfigurable chip using reconfigurable functional units is modified to better implement linear feedback shift registers. The reconfigurable functional unit has its input multiplexer unit modified so that it can select a combined value. The combined values includ... | 02/14/2006 |
| 6956878 | Method and apparatus for reducing laser speckle using polarization averaging A method and apparatus for reducing speckle uses polarization averaging. A polarizing beam splitter divides a first polarized laser output into a second polarized laser output and a third polarized laser output. A plurality of mirrors creates an optical path differe... | 10/18/2005 |
| 6956995 | Optical communication arrangement An arrangement for optical communication comprises an optical coupler, an opto-electronic board, and an optical fiber. The optical fiber comprises a first refraction surface, a second refraction surface, and an internal reflector. The first refraction surface has a ... | 10/18/2005 |
| 6947613 | Wavelength selective switch and equalizer A device comprising a light modulator including a plurality of elements wherein each element is selectively operable such that the plurality of elements are dynamically configurable to combine selected ones of a plurality of grating periods such that selected portio... | 09/20/2005 |
