Class 377/122 - Ring counter

Subclass of Class 377 - Electrical pulse counters, pulse dividers, or shift registers: circuits and systems
Definition: Subject matter where the semiconducting devices are used
No. of patents: 20
Last issue date: 07/01/2008

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Number	Title	Issue Date
7394886	Semiconductor device with latency counter A latency counter of a semiconductor device comprises a single cyclic signal generator and a command delay circuit. The single cyclic signal generator cyclically produces 0-th to n-th base signals based on an internal clock signal. The command delay circuit comprise...	07/01/2008
7280419	Latency counter having frequency detector and latency counting method thereof The present invention discloses a latency counter applied to a memory, for delaying a memory accessing control signal. The latency counter includes: a clock delay module for applying at least one delay amount to the input clock to generate a delayed input clock; a f...	10/09/2007
7268597	Self-initializing frequency divider A frequency divider apparatus is a closed loop system of a recirculating memory element, at least one feedback memory element and an end memory element in series combination. Each memory element accepts a common clock. An end memory element output is logically combi...	09/11/2007
7092480	High-speed synchronous counters with reduced logic complexity Described are fast synchronous counters with reduced combinatorial logic. In one embodiment, a four-bit shift register is configured in a ring and preset with a data pattern (e.g., 1000). The register is then rapidly shifted into any of four unique states. Combinato...	08/15/2006
7003067	High-speed synchronous counters with reduced logic complexity Described are fast synchronous counters with reduced combinatorial logic. In one embodiment, a four-bit shift register is configured in a ring and preset with a data pattern (e.g., 1000). The register is then rapidly shifted into any of four unique states. Combinato...	02/21/2006
6950490	Fault state detection mechanism for a ring-counter-based frequency divider-by-N that generates non-overlapping N-phases of divide-by-N clocks with 1/N duty ratio A fault state detector for a ring counter is formed from unit current sources each switched under the control of a different one of the outputs of the ring counter. The currents switched in that manner are passed through a unit resistance to generate a voltage signa...	09/27/2005
6879654	Non-integer frequency divider circuit A non-integer frequency divider is disclosed. The non-integer frequency divider circuit includes several base stages connected to each other. The non-integer frequency divider circuit also includes a clocking circuit for passing an enable bit from one of the base st...	04/12/2005
6826249	High-speed synchronous counters with reduced logic complexity Described are fast synchronous counters with reduced combinatorial logic. In one embodiment, a four-bit shift register is configured in a ring and preset with a data pattern (e.g., 1000). The register is then rapidly shifted into any of four unique states. Combinato...	11/30/2004
6535569	Synchronous counter A synchronous counter includes at least three or more flip-flops having a chain structure, and at least two or more 2-input EXOR gates interposed in the chain structure. The number of stages of gates interposed between the output of one among the flip-flo...	03/18/2003
6356123	Non-integer frequency divider A non-integer frequency divider that is capable of dividing an original clock frequency by a non-integer number into a desired target clock frequency. By this non-integer frequency divider, a phase-shifting circuit is first used to convert the original cl...	03/12/2002
6326824	Timing synchronizing system, devices used in the system, and timing synchronizing method An initial value generation circuit generates an initial value taking into consideration the a time delay when a signal is transmitted through the signal wires between a pilot device and other devices, and a processing delay caused in respective devices. ...	12/04/2001
6297681	Multi-cell delay generator device wherein the cells have transistor stacks and selective stack transistor bypasses A digital delay generator device is based on a series arrangement of cells, wherein each cell has a first input for receiving a single-phase clock signal, a second input for receiving a delayable signal for thereto imparting a cell delay, and an output fo...	10/02/2001
5426682	Sequential logic circuit having state hold circuits A sequential logic circuit includes N state hold circuit where N is an integer. Each of the state hold circuits has a first input terminal, a second input terminal and an output terminal. The state hold circuits are cascaded via the respective first input...	06/20/1995
5105105	High speed logic and memory family using ring segment buffer A logic and memory family using CMOS technology operates at high speeds using a Ring Segment Buffer to couple logic gates to one another in an integrated circuit chip, and to couple memory cells to other circuits to provide shift registers, triggers, cloc...	04/14/1992
5030853	High speed logic and memory family using ring segment buffer A logic and memory family using CMOS technology operates at high speeds using a Ring Segment Buffer to couple logic gates to one another in an integrated circuit chip, and to couple memory cells to other circuits to provide shift registers, triggers, cloc...	07/09/1991
4953187	High speed prescaler A high speed CMOS divide by 4/5 prescaler circuit comprises first, second, third, fourth, and fifth inverter stages. When a modulas control signal is low, the prescaler operates as five clocked inverters in series having an output which is fed back to the...	08/28/1990
4882505	Fully synchronous half-frequency clock generator A clock generating circuit having at least one loop of at least two stages. Each stage consists of a pass transistor serially connected to an inverter. An inverter couples the end of the loop to its beginning. The gate electrodes of the transistors in the...	11/21/1989
4394769	Dual modulus counter having non-inverting feedback The ring counter of this invention is self-initializing and is operable at a clock frequency corresponding to four gate delays and comprises a plurality of master of slave flip-flops, in which this high speed capability is attained by using non-inverting ...	07/19/1983
4119867	Frequency division circuit An odd number of inverting memory blocks are connected in series in a closed ring circuit. Each inverting elememt comprises a P channel field effect transistor and an N channel field effect transistor which are connected in parallel opposition. Control si...	10/10/1978
3944851	Ring counter circuit with electronic switch control of clock pulse transmission A ring counter composed of a plurality of stages connected in sequence and including electronic switches, holding circuits, and elements for feeding a timing pulse only to a stage connected after a stage which is switched on....	03/16/1976

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Class 377/122 - Ring counter